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23 条记录 (耗时 0.021 秒)

    Receiver termination circuit for a high speed direct current (DC) serial link
    13.
    发明授权
    Receiver termination circuit for a high speed direct current (DC) serial link 有权
    用于高速直流（DC）串行链路的接收器终端电路

    公开(公告)号：US07995660B2

    公开(公告)日：2011-08-09

    申请号：US11930975

    申请日：2007-10-31

    申请人： Carrie E. Cox ,  Hayden C. Cranford, Jr.

    发明人： Carrie E. Cox ,  Hayden C. Cranford, Jr.

    IPC分类号： H04B1/10 ,  H04B3/00

    CPC分类号： H04L25/0294 ,  H04L25/0276

    摘要： A method for matching receiver and transmitter common-mode voltages for a high-speed direct current (DC) serial connection between the receiver and the transmitter includes measuring, at the receiver, a common-mode voltage of the transmitter. The common-mode voltage of the transmitter is an average of a voltage signal transmitted by the transmitter and received by the receiver. The method further includes comparing the common-mode voltage of the transmitter with a common-mode voltage of the receiver. The method further includes maintaining the common-mode voltage of the receiver at a first level at which the common-mode voltage of the receiver substantially matches the common-mode voltage of the transmitter.

    摘要翻译： 用于匹配接收机和发射机之间的高速直流（DC）串行连接的接收机和发射机共模电压的方法包括在接收机处测量发射机的共模电压。 发射机的共模电压是发射机发射并由接收机接收的电压信号的平均值。 该方法还包括将发射器的共模电压与接收器的共模电压进行比较。 该方法还包括将接收器的共模电压维持在接收器的共模电压基本上与发射机的共模电压相匹配的第一电平。

    RECEIVER TERMINATION CIRCUIT FOR A HIGH SPEED DIRECT CURRENT (DC) SERIAL LINK
    14.
    发明申请
    RECEIVER TERMINATION CIRCUIT FOR A HIGH SPEED DIRECT CURRENT (DC) SERIAL LINK 有权
    用于高速直流电（DC）串行链路的接收终端电路

    公开(公告)号：US20090110084A1

    公开(公告)日：2009-04-30

    申请号：US11930975

    申请日：2007-10-31

    申请人： Carrie E. Cox ,  Hayden C. Cranford, JR.

    发明人： Carrie E. Cox ,  Hayden C. Cranford, JR.

    IPC分类号： H04L25/00

    CPC分类号： H04L25/0294 ,  H04L25/0276

    摘要： A method for matching receiver and transmitter common-mode voltages for a high-speed direct current (DC) serial connection between the receiver and the transmitter includes measuring, at the receiver, a common-mode voltage of the transmitter. The common-mode voltage of the transmitter is an average of a voltage signal transmitted by the transmitter and received by the receiver. The method further includes comparing the common-mode voltage of the transmitter with a common-mode voltage of the receiver. The method further includes maintaining the common-mode voltage of the receiver at a first level at which the common-mode voltage of the receiver substantially matches the common-mode voltage of the transmitter.

    摘要翻译： 用于匹配接收机和发射机之间的高速直流（DC）串行连接的接收机和发射机共模电压的方法包括在接收机处测量发射机的共模电压。 发射机的共模电压是发射机发射并由接收机接收的电压信号的平均值。 该方法还包括将发射器的共模电压与接收器的共模电压进行比较。 该方法还包括将接收器的共模电压维持在接收器的共模电压基本上与发射机的共模电压相匹配的第一电平。

    Impedance Calibration for Source Series Terminated Serial Link Transmitter
    16.
    发明申请
    Impedance Calibration for Source Series Terminated Serial Link Transmitter 失效
    源串联终端串行链路发射机的阻抗校准

    公开(公告)号：US20080120838A1

    公开(公告)日：2008-05-29

    申请号：US12028439

    申请日：2008-02-08

    申请人： Steven M. Clements ,  William P. Cornwell ,  Carrie E. Cox ,  Hayden C. Cranford ,  Vernon R. Norman

    发明人： Steven M. Clements ,  William P. Cornwell ,  Carrie E. Cox ,  Hayden C. Cranford ,  Vernon R. Norman

    IPC分类号： H01R43/00

    CPC分类号： G01R35/007 ,  Y10T29/49004 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T29/49174

    摘要： Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.

    摘要翻译： 将被测器件（DUT）的输出阻抗基本上精确地校准到允许阻抗的预定范围内。 DUT是源极串行端接（SST）串行链路发射机的一部分，其中当并联支路的特定晶体管导通时，并联晶体管的两个分支都提供阻抗值。 将阻抗值加到串联电阻器上以提供输出阻抗。 DUT由与电阻器串联的并行晶体管的一个分支组成。 将DUT的输出阻抗与参考电阻的电阻进行比较，并且比较器根据输出阻抗是否落在参考电阻的预设百分比方差内提供控制信号。 控制信号由FSM（有限状态机）进行处理，FSM单独打开或关闭并联支路内的晶体管，直到DUT阻抗值落在所需范围内。

    SOURCE SERIES TERMINATED DRIVER CIRCUIT WITH PROGRAMMABLE OUTPUT RESISTANCE, AMPLITUDE REDUCTION, AND EQUALIZATION
    19.
    发明申请
    SOURCE SERIES TERMINATED DRIVER CIRCUIT WITH PROGRAMMABLE OUTPUT RESISTANCE, AMPLITUDE REDUCTION, AND EQUALIZATION 失效
    源可编程驱动器电路，具有可编程输出电阻，幅度降低和均衡

    公开(公告)号：US20130335120A1

    公开(公告)日：2013-12-19

    申请号：US13526725

    申请日：2012-06-19

    申请人： John J. Bergkvist, JR. ,  Carrie E. Cox ,  Todd E. Leonard

    发明人： John J. Bergkvist, JR. ,  Carrie E. Cox ,  Todd E. Leonard

    IPC分类号： H03K3/01

    CPC分类号： H03K19/00 ,  H03K19/018557 ,  H03K19/018585

    摘要： A source-series terminated (‘SST’) driver circuit that includes: one or more data signal inputs; one or more control signal inputs; a driver output; and a plurality of driver cells, the driver cells coupled in parallel to one another, outputs of the driver cells coupled together to form the driver output of the SST driver circuit, where output resistance of the SST driver circuit varies in dependence upon activation of one or more of the parallel driver cells, activation of each driver cell controlled by control signals received at the control signal inputs.

    摘要翻译： 源极端接（'SST'）驱动电路，包括：一个或多个数据信号输入; 一个或多个控制信号输入; 驱动器输出; 以及多个驱动器单元，所述驱动器单元彼此并联耦合，所述驱动器单元的输出耦合在一起以形成所述SST驱动器电路的驱动器输出，其中所述SST驱动器电路的输出电阻根据一个 或更多的并行驱动器单元，通过在控制信号输入处接收的控制信号来控制每个驱动单元的激活。