利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

44 条记录 (耗时 0.037 秒)

    SOURCE SERIES TERMINATED DRIVER CIRCUIT WITH PROGRAMMABLE OUTPUT RESISTANCE, AMPLITUDE REDUCTION, AND EQUALIZATION
    1.
    发明申请
    SOURCE SERIES TERMINATED DRIVER CIRCUIT WITH PROGRAMMABLE OUTPUT RESISTANCE, AMPLITUDE REDUCTION, AND EQUALIZATION 失效
    源可编程驱动器电路，具有可编程输出电阻，幅度降低和均衡

    公开(公告)号：US20130335120A1

    公开(公告)日：2013-12-19

    申请号：US13526725

    申请日：2012-06-19

    申请人： John J. Bergkvist, JR. ,  Carrie E. Cox ,  Todd E. Leonard

    发明人： John J. Bergkvist, JR. ,  Carrie E. Cox ,  Todd E. Leonard

    IPC分类号： H03K3/01

    CPC分类号： H03K19/00 ,  H03K19/018557 ,  H03K19/018585

    摘要： A source-series terminated (‘SST’) driver circuit that includes: one or more data signal inputs; one or more control signal inputs; a driver output; and a plurality of driver cells, the driver cells coupled in parallel to one another, outputs of the driver cells coupled together to form the driver output of the SST driver circuit, where output resistance of the SST driver circuit varies in dependence upon activation of one or more of the parallel driver cells, activation of each driver cell controlled by control signals received at the control signal inputs.

    摘要翻译： 源极端接（'SST'）驱动电路，包括：一个或多个数据信号输入; 一个或多个控制信号输入; 驱动器输出; 以及多个驱动器单元，所述驱动器单元彼此并联耦合，所述驱动器单元的输出耦合在一起以形成所述SST驱动器电路的驱动器输出，其中所述SST驱动器电路的输出电阻根据一个 或更多的并行驱动器单元，通过在控制信号输入处接收的控制信号来控制每个驱动单元的激活。

    Source series terminated driver circuit with programmable output resistance, amplitude reduction, and equalization
    2.
    发明授权
    Source series terminated driver circuit with programmable output resistance, amplitude reduction, and equalization 失效
    源极串联驱动电路具有可编程输出电阻，幅度降低和均衡

    公开(公告)号：US08618833B1

    公开(公告)日：2013-12-31

    申请号：US13526725

    申请日：2012-06-19

    申请人： John J. Bergkvist, Jr. ,  Carrie E. Cox ,  Todd E. Leonard

    发明人： John J. Bergkvist, Jr. ,  Carrie E. Cox ,  Todd E. Leonard

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/00 ,  H03K19/018557 ,  H03K19/018585

    摘要： A source-series terminated (‘SST’) driver circuit that includes: one or more data signal inputs; one or more control signal inputs; a driver output; and a plurality of driver cells, the driver cells coupled in parallel to one another, outputs of the driver cells coupled together to form the driver output of the SST driver circuit, where output resistance of the SST driver circuit varies in dependence upon activation of one or more of the parallel driver cells, activation of each driver cell controlled by control signals received at the control signal inputs.

    摘要翻译： 源极端接（'SST'）驱动电路，包括：一个或多个数据信号输入; 一个或多个控制信号输入; 驱动器输出; 以及多个驱动器单元，所述驱动器单元彼此并联耦合，所述驱动器单元的输出耦合在一起以形成所述SST驱动器电路的驱动器输出，其中所述SST驱动器电路的输出电阻根据一个 或更多的并行驱动器单元，通过在控制信号输入处接收的控制信号来控制每个驱动单元的激活。

    On-chip identification circuit incorporating pairs of conductors, each having an essentially random chance of being shorted together as a result of process variations
    3.
    发明授权
    On-chip identification circuit incorporating pairs of conductors, each having an essentially random chance of being shorted together as a result of process variations 有权
    集成了导体对的片上识别电路，每个导体具有由于工艺变化而基本上随机的短路的机会

    公开(公告)号：US08291357B2

    公开(公告)日：2012-10-16

    申请号：US11869179

    申请日：2007-10-09

    申请人： Serafino Bueti ,  Adam J. Courchesne ,  Kenneth J. Goodnow ,  Todd E. Leonard ,  Peter A. Sandon ,  Peter A. Twombly ,  Charles S. Woodruff

    发明人： Serafino Bueti ,  Adam J. Courchesne ,  Kenneth J. Goodnow ,  Todd E. Leonard ,  Peter A. Sandon ,  Peter A. Twombly ,  Charles S. Woodruff

    IPC分类号： G06F9/45

    CPC分类号： H01L23/544 ,  H01L23/5286 ,  H01L2223/5444 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/00

    摘要： Disclosed are embodiments of on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e., an approximately 50/50 chance) of a short. In another embodiment different masks form first conductors (e.g., metal lines separated by varying distances and having different widths) and second conductors (e.g., metal vias separated by varying distances and having equal widths). The first and second conductors alternate across the chip. Due to the different separation distances and widths of the first conductors, the different separation distances of the second conductors and, random mask alignment variations, each first conductor can short to up to two second conductors. In each embodiment the resulting pattern of shorts and opens, can be used as an on-chip identifier or private key.

    摘要翻译： 公开了片上识别电路的实施例。 在一个实施例中，在一个或多个金属化层内形成导体对（例如，金属焊盘，通孔，线）。 每对中的导体之间的距离是预先确定的，因此，在已知的跨越芯片线的变化中，存在短路的随机机会（即，大约50/50的几率）。 在另一个实施例中，不同的掩模形成第一导体（例如，由变化的距离分隔并具有不同宽度的金属线）和第二导体（例如，通过变化的距离分开并具有相等宽度的金属通孔）。 第一和第二导体在芯片之间交替。 由于第一导体的分离距离和宽度不同，第二导体的不同间隔距离和随机掩模对准变化，每个第一导体可以短至多达两个第二导体。 在每个实施例中，所得到的短路和开路模式可用作片上标识符或私钥。

    Method for monitoring BER in an infiniband environment
    5.
    发明授权
    Method for monitoring BER in an infiniband environment 失效
    监测无限环境中BER的方法

    公开(公告)号：US07715323B2

    公开(公告)日：2010-05-11

    申请号：US11750846

    申请日：2007-05-18

    申请人： Brian J. Connolly ,  Todd E. Leonard

    发明人： Brian J. Connolly ,  Todd E. Leonard

    IPC分类号： H04J1/16 ,  G06F11/00

    CPC分类号： H04J3/047 ,  H04L1/0026 ,  H04L1/0033 ,  H04L1/20 ,  H04L25/03343 ,  H04L47/38

    摘要： A method is disclosed for tuning each channel of a high-speed SerDes cable link interface arranged in a configuration linking a local side physical layer to a remote side physical layer. The method includes initiating an operational state of high-speed SerDes cable link interface, identifying flow-control packet Op codes not cited for use by operational high-speed SerDes cable link interface, transmitting a flow control signal from the local side physical layer to the remote side physical layer to control the remote side physical layer to monitor the bit error rate (BER) of the channels used by the local side physical layer to transfer data to the remote side physical layer, monitoring the BER in the channels used for data transfer, transferring BER data acquired in the monitoring to the local side physical layer and processing the BER data by the local side physical layer to generate equalization setting adjustments.

    摘要翻译： 公开了一种用于调整以将本地侧物理层与远端物理层相连的配置布置的高速SerDes电缆链路接口的每个信道进行调谐的方法。 该方法包括启动高速SerDes电缆链路接口的操作状态，识别未被引用为操作高速SerDes电缆链路接口使用的流量控制分组Op码，将流控制信号从本地物理层发送到 远程物理层控制远程物理层，以监视本地物理层使用的信道的误码率（BER），将数据传输到远程物理层，监控用于数据传输的信道的BER 将在监视中获取的BER数据传送到本地物理层，并通过本地侧物理层处理BER数据，以产生均衡设置调整。

    SYSTEM AND METHOD FOR IMPROVING EQUALIZATION IN A HIGH SPEED SERDES ENVIRONMENT
    6.
    发明申请
    SYSTEM AND METHOD FOR IMPROVING EQUALIZATION IN A HIGH SPEED SERDES ENVIRONMENT 审中-公开
    用于改进高速串行环境中均衡化的系统和方法

    公开(公告)号：US20090245110A1

    公开(公告)日：2009-10-01

    申请号：US12056386

    申请日：2008-03-27

    申请人： Brian J. Connolly ,  Todd E. Leonard

    发明人： Brian J. Connolly ,  Todd E. Leonard

    IPC分类号： H04J3/16

    CPC分类号： H04L25/03

    摘要： A method and accompanying system are disclosed for tuning each channel of a high-speed SerDes link interface arranged in a configuration linking a local side to a remote side. The method includes transmitting a flow control packets from the local side to the remote side to change remote side transmission characteristics in a link channel; monitoring signal eye characteristics in the link channel; transferring additional flow control packets to adjust the remote side transmission characteristics; and processing the signal eye characteristics at the local side to generate the remote side transmission characteristics for the link channel.

    摘要翻译： 公开了一种方法和附带系统，用于调整以将本地侧连接到远程侧的配置布置的高速SerDes链路接口的每个信道。 该方法包括从本地侧向远程侧发送流量控制分组，以改变链路信道中的远端传输特性; 监控链路信道中的信号眼特性; 传输额外的流量控制包以调整远端传输特性; 并处理本地的信号眼特性，以生成链路信道的远端传输特性。

    TASK BASED DEBUGGER (TRANSACATION-EVENT-JOB-TRIGGER)
    8.
    发明申请
    TASK BASED DEBUGGER (TRANSACATION-EVENT-JOB-TRIGGER) 失效
    基于任务调度器（交易活动 - 工作触发器）

    公开(公告)号：US20080127216A1

    公开(公告)日：2008-05-29

    申请号：US11461793

    申请日：2006-08-02

    申请人： Serafino Bueti ,  Kenneth J. Goodnow ,  Todd E. Leonard ,  Grogory J. Mann ,  Charles S. Woodruff

    发明人： Serafino Bueti ,  Kenneth J. Goodnow ,  Todd E. Leonard ,  Grogory J. Mann ,  Charles S. Woodruff

    IPC分类号： G06F3/00

    CPC分类号： G06F17/5022 ,  G06F15/7842 ,  G06F2217/14

    摘要： The embodiments of the invention provide an apparatus, method, etc. for a task based debugger (transaction-event-job-trigger). More specifically, an integrated event monitor for a SOC comprises functional cores each having a functional debug logic element. The cores are connected to an interconnect structure that links the functional debug logic elements. Each functional debug logic element is specifically dedicated to a function of its corresponding core, wherein the functional debug logic elements generate a table of function-specific system events. The system events are function-specific with respect to an associated core, wherein the system events include transaction events, controller events, processor events, interconnect structure arbiter events, interconnect interface core events, high speed serial link core events, and/or codec events.

    摘要翻译： 本发明的实施例提供了一种用于基于任务的调试器（事务 - 事件 - 作业触发）的装置，方法等。 更具体地，SOC的集成事件监视器包括各自具有功能调试逻辑元件的功能核心。 核心连接到链接功能调试逻辑元件的互连结构。 每个功能调试逻辑元件专门用于其相应核心的功能，其中功能调试逻辑元件产生功能特定系统事件表。 系统事件相对于相关联的核心是特定于功能的，其中系统事件包括交易事件，控制器事件，处理器事件，互连结构仲裁器事件，互连接口核心事件，高速串行链路核心事件和/或编解码器事件 。

    System-on-chip (SOC), design structure and method
    10.
    发明授权
    System-on-chip (SOC), design structure and method 有权
    片上系统（SOC），设计结构和方法

    公开(公告)号：US07904873B2

    公开(公告)日：2011-03-08

    申请号：US12125269

    申请日：2008-05-22

    申请人： Jonathan P. Ebbers ,  Todd E. Leonard ,  Kyle E. Schneider ,  Peter A. Twombly

    发明人： Jonathan P. Ebbers ,  Todd E. Leonard ,  Kyle E. Schneider ,  Peter A. Twombly

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F2217/66

    摘要： Disclosed is a system-on-chip (SOC) structure that allows for automated integration of multiple intellectual cores. The SOC structure incorporates a plurality of cells connected to a common bus on a chip. Each cell incorporates a functional core and an automated integration unit (AIU) connected to the functional core. Each AIU communicates integration information for its functional core over the common bus to the AIUs in the other cells. The exchange of information between the AIUs is controlled either by the integration units themselves or by a controller. Based on received integration information, each AIU can automatically make any required configuration adjustments for integration. Furthermore, based on this exchange of information, the functional cores can interact, as necessary, during SOC operation. Also disclosed are an associated method of forming such a SOC structure and a design structure for such an SOC structure.

    摘要翻译： 公开了一种片上系统（SOC）结构，允许多个智能核心的自动化集成。 SOC结构包括连接到芯片上的公共总线的多个单元。 每个单元结合功能核心和连接到功能核心的自动化集成单元（AIU）。 每个AIU通过公共总线将其功能核心的集成信息传送到其他单元中的AIU。 AIU之间的信息交换由集成单元本身或控制器控制。 基于接收的集成信息，每个AIU可以自动进行任何必要的配置调整进行集成。 此外，基于这种信息交换，功能核心可以根据需要在SOC操作期间进行交互。 还公开了形成这种SOC结构的相关方法和用于这种SOC结构的设计结构。