公开(公告)号：US4189772A

公开(公告)日：1980-02-19

申请号：US887095

申请日：1978-03-16

申请人： John S. Liptay

发明人： John S. Liptay

IPC分类号： G06F9/308 ,  G06F9/34 ,  G06F9/345 ,  G06F9/38 ,  G06F12/04 ,  G06F12/08 ,  G06F1/00

CPC分类号： G06F9/30018 ,  G06F12/04 ,  G06F12/0859 ,  G06F12/0886 ,  G06F9/345 ,  G06F9/383

摘要： Operand controls are provided in an I-unit which includes a plurality of address operand pairs (AOP's). Each AOP has an operand request register and an operand buffer. The AOP's are used to fetch the subline (e.g. doubleword) of operands in variable length field (VLF) instructions (such as LM, MVC, CLC, XC, etc.). Each AOP is capable of requesting and receiving a single subline fetched by a storage control. Each AOP buffers its received subline until needed for executing the instruction. The bytes of VLF operands are not aligned on subline boundaries. The AOP's are dynamically selected to fetch the sublines of current operand(s). The AOP's selected for a single operand are sequenced by a chain of back pointers held in latches, which respectively represent the AOP's. Each latch receives the identifier (ID) of the previous AOP in the chain for the operand. An associative search through the previous ID's in all latches obtains the forward order of AOP ID's. The AOP's are selected, started, and released dynamically so that the same AOP may be used more than once for different sublines of a single operand. Two AOP's receive the same first fetch request for an operand when required for operand alignment.

摘要翻译： 在包括多个地址操作数对（AOP））的I单元中提供操作数控制。 每个AOP都有一个操作数请求寄存器和一个操作数缓冲区。 AOP用于获取可变长度字段（VLF）指令（例如LM，MVC，CLC，XC等）中的操作数的子线（例如双字）。 每个AOP能够请求和接收由存储控制器提取的单个子集。 每个AOP缓冲其接收到的子线，直到执行指令为止。 VLF操作数的字节在子行边界上不对齐。 动态选择AOP以获取当前操作数的子集。 选择用于单个操作数的AOP由锁定器中分别表示AOP的后向指针链排序。 每个锁存器接收操作数链中先前AOP的标识符（ID）。 在所有锁存器中通过先前ID的关联搜索获得AOP ID的转发顺序。 动态地选择，启动和释放AOP，使得相同的AOP可以不止一次地用于单个操作数的不同子系统。 当操作数对齐需要时，两个AOP接收到与操作数相同的第一次提取请求。

公开(公告)号：US06745313B2

公开(公告)日：2004-06-01

申请号：US10042533

申请日：2002-01-09

申请人： John S. Liptay ,  Mark A. Check ,  Brian R. Prasky ,  Chung-Lung Kevin Shum

发明人： John S. Liptay ,  Mark A. Check ,  Brian R. Prasky ,  Chung-Lung Kevin Shum

IPC分类号： G06F1200

CPC分类号： G06F12/0862 ,  G06F12/1054 ,  G06F2212/6024

摘要： A method is disclosed for selecting data in a computer system having a cache memory and a branch history table, where the method includes predicting an address corresponding to the data, selecting data at the predicted address in the cache memory, translating an address corresponding to the data, comparing the translated address with the predicted address, and if they are different, re-selecting data at the translated address in the cache memory and appending the translated address to the branch history table.

摘要翻译： 公开了一种用于在具有高速缓冲存储器和分支历史表的计算机系统中选择数据的方法，其中该方法包括预测对应于该数据的地址，在高速缓冲存储器中选择预测地址处的数据， 数据，将转换的地址与预测地址进行比较，如果它们不同，则在高速缓冲存储器中的翻译地址处重新选择数据，并将转换的地址附加到分支历史表。

公开(公告)号：US4901233A

公开(公告)日：1990-02-13

申请号：US75483

申请日：1987-07-20

申请人： John S. Liptay

发明人： John S. Liptay

IPC分类号： G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G11C11/419

CPC分类号： G06F9/3855 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3863 ,  G11C11/419

摘要： A register management system has more physical registers for general purpose use than are named in the architectural system. A renaming system identifies particular physical registers to perform as architected addressable or general purpose registers. An array control list (ACL) is provided to monitor the assignment and status of the physical registers. A decode register assignment list (DRAL) is provided to monitor the status of all of the architected registers and the correspondence to physical registers. A back-up register assignment list (BRAL) is used to preserve old status information while out of sequence and conditional branch instructions are executed. The physical registers may retain mutliple copies of individual addressable registers representing the contents at different stages of execution. The addressable register status may be restored if instruction execution is out of sequence or on a conditional branch causing a problem requiring restoration. The register management system may be used in a processor having multiple execution units of different types.

公开(公告)号：US06671794B1

公开(公告)日：2003-12-30

申请号：US09678226

申请日：2000-10-02

申请人： Bruce C. Giamei ,  Mark A. Check ,  John S. Liptay

发明人： Bruce C. Giamei ,  Mark A. Check ,  John S. Liptay

IPC分类号： G06F938

CPC分类号： G06F9/3838 ,  G06F9/3824 ,  G06F9/3836

摘要： A method and system for detecting address generation interlock in a pipelined data processor is disclosed. The method comprises accumulating a plurality of vectors over a predefined number of processor clock cycles, with subsequent vectors corresponding to subsequent clock cycles; accumulating the status of one or more general registers in the plurality of vectors with the same bit location in each vector of the plurality of vectors corresponding to a particular general register; generating a list of pending general register updates from a logical combination of the plurality of vectors; and determining the existence of address generation interlock from the list of pending general register updates.

摘要翻译： 公开了一种在流水线数据处理器中检测地址生成互锁的方法和系统。 该方法包括在预定数量的处理器时钟周期上累积多个向量，后续矢量对应于随后的时钟周期; 在对应于特定通用寄存器的多个向量中的每个向量中的相同比特位置累积多个向量中的一个或多个通用寄存器的状态; 从所述多个向量的逻辑组合生成待决通用寄存器更新的列表; 并从挂起的通用寄存器更新列表中确定地址生成互锁的存在。

公开(公告)号：US4200927A

公开(公告)日：1980-04-29

申请号：US866686

申请日：1978-01-03

申请人： Jeffrey F. Hughes ,  John S. Liptay ,  James W. Rymarczyk ,  Stanley E. Stone

发明人： Jeffrey F. Hughes ,  John S. Liptay ,  James W. Rymarczyk ,  Stanley E. Stone

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/00

CPC分类号： G06F9/382 ,  G06F9/3804 ,  G06F9/3846 ,  G06F9/3851 ,  G06F9/3889

摘要： In a high-performance computer which prefetches and predecodes instructions for sequential presentation to an execution unit, at least three separately gated and sequenced multi-instruction buffers for prefetched instructions permit continued sequential predecoding and buffering of instructions from three independent instruction streams identified by multiple branch instructions, some of which may be conditionally executed. A number of stored pointers identify particular ones of the multiple instruction buffers. Various branch instructions are predicted to be successful or unsuccessful. Result signals from the instruction execution unit, in response to execution of conditional branch instructions, will control the setting of various pointers and busy triggers associated with each instruction buffer, causing the next sequential instruction transferred to the instruction execution unit to be from the proper instruction stream based on the result of the branch on condition instruction.

摘要翻译： 在预取和预解码用于顺序呈现到执行单元的指令的高性能计算机中，用于预取指令的至少三个单独门控和顺序的多指令缓冲器允许来自由多个分支标识的三个独立指令流的指令的继续顺序预解码和缓冲 指令，其中一些可能有条件地执行。 多个存储的指针标识多个指令缓冲器中的特定的指针。 预测各种分支指令是成功的还是不成功的。 来自指令执行单元的响应于条件分支指令的执行的结果信号将控制与每个指令缓冲器相关联的各种指针和忙触发器的设置，使得传送到指令执行单元的下一个顺序指令来自正确的指令 基于条件指令的分支结果流。

公开(公告)号：US4189770A

公开(公告)日：1980-02-19

申请号：US887097

申请日：1978-03-16

申请人： Patrick M. Gannon ,  John S. Liptay

发明人： Patrick M. Gannon ,  John S. Liptay

IPC分类号： G06F9/308 ,  G06F9/312 ,  G06F9/34 ,  G06F9/38 ,  G06F12/04 ,  G06F12/08 ,  G06F1/00

CPC分类号： G06F9/30018 ,  G06F12/04 ,  G06F12/0859 ,  G06F12/0886 ,  G06F9/30043 ,  G06F9/383

摘要： In the case of a cache miss, the successive fetch requests by the I-unit for sublines (e.g. doublewords) of a variable length field operand are provided by the first through the highest-address fetched sublines in a line being accessed from main storage via a cache bypass. This avoids the time delay for the I-unit caused by waiting until the complete line has been transferred to the cache before all required sublines in the line are obtainable from the cache. Address operand pairs (AOP's) consisting of request and buffer registers are provided in the I-unit to handle the fetched sublines as fast as the cache bypass can provide them from main storage. If there is a cache hit, the sublines are accessed from the cache.

摘要翻译： 在高速缓存未命中的情况下，由可变长度字段操作数的子单元（例如双字）的I单元的连续提取请求由从主存储器经由主存储器访问的行中的第一到最高地址获取的子行提供 缓存旁路。 这避免了在缓存中可以获得所有必需的子线之前等待直到完整的线路传输到缓存器为止导致I单元的时间延迟。 在I单元中提供由请求和缓冲寄存器组成的地址操作数对（AOP），以便缓存旁路可以从主存储器提供它们来处理获取的子行。 如果有缓存命中，则从高速缓存访​​问子系统。

公开(公告)号：US4189768A

公开(公告)日：1980-02-19

申请号：US887091

申请日：1978-03-16

申请人： John S. Liptay ,  James W. Rymarczyk

发明人： John S. Liptay ,  James W. Rymarczyk

IPC分类号： G06F9/308 ,  G06F9/34 ,  G06F9/345 ,  G06F9/38 ,  G06F12/04 ,  G06F12/08 ,  G06F1/00

CPC分类号： G06F9/30018 ,  G06F12/04 ,  G06F12/0859 ,  G06F12/0886 ,  G06F9/345 ,  G06F9/383

摘要： Operand controls are provided in an I-unit using address operand pairs (AOPs), each pair consisting of a request register and a buffer register. When handling variable field length (VFL) instructions with source (SRC) and destination (DST) operand addresses, two AOPs are generally assigned to receive different parts of the first subline (e.g. doubleword) of the SRC operand; this is called a duplicate fetch and is used with any size VFL operand. Efficiency is improved for the special case in which the DST operand has all of its bytes confined to a single subline in main storage by detecting the special case and inhibiting a duplicate fetch signal to the I-unit controls which assign duplicate AOPs to an instruction. The SRC operand may have more than one subline but the alignment controls force all source operand bytes into a single subline for the special case. When the duplicate fetch signal is suppressed, only one AOP is assigned by the controls to the first subline fetch for the SRC operand.

摘要翻译： 操作数控制在I单元中使用地址操作数对（AOP）提供，每对由请求寄存器和缓冲寄存器组成。 当处理具有源（SRC）和目的地（DST）操作数地址的可变字段长度（VFL）指令时，通常分配两个AOP以接收SRC操作数的第一子线（例如双字）的不同部分; 这被称为重复提取，并与任何大小的VFL操作数一起使用。 对于特殊情况，DST操作数将其所有字节限制在主存储器中的单个子线路上的特殊情况，通过检测特殊情况并禁止将重复的提取信号分配给指令的重复AOP的I单元控制，特效的效率得到改善。 SRC操作数可能有多个子行，但是对齐控件会将所有源操作数字节强制为特殊情况的单个子行。 当重复提取信号被抑制时，控制器只将一个AOP分配给SRC操作数的第一个子线取出。