Absolute address bits kept in branch history table
    1.
    发明授权
    Absolute address bits kept in branch history table 有权
    绝对地址位保存在分支历史表中

    公开(公告)号:US06745313B2

    公开(公告)日:2004-06-01

    申请号:US10042533

    申请日:2002-01-09

    IPC分类号: G06F1200

    摘要: A method is disclosed for selecting data in a computer system having a cache memory and a branch history table, where the method includes predicting an address corresponding to the data, selecting data at the predicted address in the cache memory, translating an address corresponding to the data, comparing the translated address with the predicted address, and if they are different, re-selecting data at the translated address in the cache memory and appending the translated address to the branch history table.

    摘要翻译: 公开了一种用于在具有高速缓冲存储器和分支历史表的计算机系统中选择数据的方法,其中该方法包括预测对应于该数据的地址,在高速缓冲存储器中选择预测地址处的数据, 数据,将转换的地址与预测地址进行比较,如果它们不同,则在高速缓冲存储器中的翻译地址处重新选择数据,并将转换的地址附加到分支历史表。

    Read only store as part of cache store for storing frequently used
millicode instructions
    3.
    发明授权
    Read only store as part of cache store for storing frequently used millicode instructions 失效
    只读存储作为缓存存储的一部分,用于存储常用的millicode指令

    公开(公告)号:US5625808A

    公开(公告)日:1997-04-29

    申请号:US455820

    申请日:1995-05-31

    IPC分类号: G06F9/318 G06F9/38 G06F9/22

    CPC分类号: G06F9/3802 G06F9/3017

    摘要: A read only storage (ROS) array holds a small set of relatively simple millicode instructions; those millicode instruction routines which are most commonly called on in executing common application workloads. The millicode read only store is implemented as a portion of hardware system area (HSA) storage. The cache control includes a register which contains hardware system area address corresponding to the read only store address. When an instruction fetch request is received by the cache control, the absolute address of the instruction fetch request is compared with the read only store address in the register in parallel with the normal cache directory lookup. If the instruction fetch request matches the read only store address, the fetch is made from the read only store independently of the directory lookup result.

    摘要翻译: 只读存储(ROS)阵列包含一小组相对简单的millicode指令; 那些在执行常见应用程序工作负载中最常调用的那些millicode指令例程。 millicode只读存储器实现为硬件系统区域(HSA)存储的一部分。 高速缓存控制包括一个寄存器,该寄存器包含与只读存储地址对应的硬件系统区域地址。 当缓存控制接收到指令提取请求时,将指令提取请求的绝对地址与正常缓存目录查找并行地与寄存器中的只读存储地址进行比较。 如果指令提取请求与只读存储地址相匹配,则从独立于目录查找结果的只读存储进行读取。

    Method for ensuring that a line is present in an instruction cache
    4.
    发明授权
    Method for ensuring that a line is present in an instruction cache 有权
    确保指令缓存中存在一行的方法

    公开(公告)号:US06751708B2

    公开(公告)日:2004-06-15

    申请号:US10042534

    申请日:2002-01-09

    IPC分类号: G06F1200

    摘要: A method is disclosed for instructing a computing system to ensure that a line is present in an instruction cache that includes selecting a line-touch instruction, recognizing the line-touch instruction as a type of branch instruction where the branch is not taken, executing the line-touch instruction to fetch a target line from a target address into the instruction cache, and interlocking the execution of the line-touch instruction with the completion of the fetch of the target line in order to prevent execution of the instruction following the line-touch instruction until after the target line has reached the cache.

    摘要翻译: 公开了一种用于指示计算系统确保线路存在于指令高速缓存中的方法,所述指令高速缓存包括选择行触摸指令,将线接触指令识别为不采用分支的分支指令的类型,执行 线接触指令,用于从目标地址获取目标行到指令高速缓存中,并且将行触摸指令的执行与目标行的获取完成互锁,以防止执行跟踪行指令之后的指令, 触摸指令,直到目标行到达缓存。

    Address generation interlock detection
    5.
    发明授权
    Address generation interlock detection 有权
    地址生成互锁检测

    公开(公告)号:US06671794B1

    公开(公告)日:2003-12-30

    申请号:US09678226

    申请日:2000-10-02

    IPC分类号: G06F938

    摘要: A method and system for detecting address generation interlock in a pipelined data processor is disclosed. The method comprises accumulating a plurality of vectors over a predefined number of processor clock cycles, with subsequent vectors corresponding to subsequent clock cycles; accumulating the status of one or more general registers in the plurality of vectors with the same bit location in each vector of the plurality of vectors corresponding to a particular general register; generating a list of pending general register updates from a logical combination of the plurality of vectors; and determining the existence of address generation interlock from the list of pending general register updates.

    摘要翻译: 公开了一种在流水线数据处理器中检测地址生成互锁的方法和系统。 该方法包括在预定数量的处理器时钟周期上累积多个向量,后续矢量对应于随后的时钟周期; 在对应于特定通用寄存器的多个向量中的每个向量中的相同比特位置累积多个向量中的一个或多个通用寄存器的状态; 从所述多个向量的逻辑组合生成待决通用寄存器更新的列表; 并从挂起的通用寄存器更新列表中确定地址生成互锁的存在。

    System and Method to Support Use of Bus Spare Wires in Connection Modules
    7.
    发明申请
    System and Method to Support Use of Bus Spare Wires in Connection Modules 失效
    支持在连接模块中使用总线备用线的系统和方法

    公开(公告)号:US20080082878A1

    公开(公告)日:2008-04-03

    申请号:US11531430

    申请日:2006-09-13

    IPC分类号: G01R31/28

    CPC分类号: G01R31/31855 G01R31/31717

    摘要: In a computer system with multiple chips connected via a connection module with high speed elastic interface buses that support bus repair is enhanced by use of a spare net. Support is provided to ensure that the spare net can be tested in the same way that every normal bus net can be tested at all supported environments. It ensure that the system controller can find out what connections are bad and how to apply the controls to repair them for all tests and in the field for the customer.

    摘要翻译: 在具有通过连接模块连接的多个芯片的计算机系统中,通过使用备用网络来增强支持总线修理的高速弹性接口总线。 提供支持,以确保备用网络的测试方式与每个正常总线网络在所有支持环境下都可以进行测试相同。 它确保系统控制器可以找出哪些连接不好,以及如何应用控件来对所有测试进行修复,并为客户提供现场维护。

    Re-fetch of long operand buffered remainder after cache line invalidation in out-of-order multiprocessor system without instruction re-execution
    8.
    发明授权
    Re-fetch of long operand buffered remainder after cache line invalidation in out-of-order multiprocessor system without instruction re-execution 失效
    在无指令重新执行的无序多处理器系统中,在高速缓存行无效之后重新获取长操作数缓冲余数

    公开(公告)号:US07089408B2

    公开(公告)日:2006-08-08

    申请号:US10435879

    申请日:2003-05-12

    IPC分类号: G06F9/34

    CPC分类号: G06F9/383 G06F9/3861

    摘要: A system and method to re-fetch operand data lost for instructions with operands greater than eight bytes in length due to line invalidation due to storage update from a single or plurality of processors in a multiprocessor computer system using microprocessors that perform out of order operand fetch with respect to sequential program order in which it is not possible or desirable to kill the execution of the instruction when the storage access rules require that it appear that the operand data is accessed in program execution order.

    摘要翻译: 由于多处理器计算机系统中的单个或多个处理器的存储更新导致线路无效,因此使用执行无序操作数获取的微处理器,重新获取长度大于8字节的指令的操作数丢失的系统和方法 关于顺序程序顺序,其中当存储访问规则要求看起来以程序执行顺序访问操作数数据时,不可能或不希望地杀死指令的执行。

    System and method for simultaneous access of the same doubleword in cache storage
    9.
    发明授权
    System and method for simultaneous access of the same doubleword in cache storage 失效
    高速缓存存储中同一双字的同时访问的系统和方法

    公开(公告)号:US06990556B2

    公开(公告)日:2006-01-24

    申请号:US10436221

    申请日:2003-05-12

    IPC分类号: G06F12/00

    摘要: An embodiment of the invention is a processor for providing simultaneous access to the same data for a plurality of requests. The processor includes cache storage having an address sliced directory lookup structure. A same doubleword detection unit receives a first instruction including a plurality of first instruction fields on a first pipe and a second instruction including a plurality of second instruction fields on a second pipe. The same doubleword detection unit generates a same doubleword signal in response to the first instruction fields and the second instruction fields. The cache storage reads data from a single doubleword in the cache storage and simultaneously provides the doubleword to the first pipe and the second pipe in response to the same doubleword signal.

    摘要翻译: 本发明的一个实施例是用于提供对多个请求的同一数据的同时访问的处理器。 处理器包括具有地址分片目录查找结构的高速缓冲存储器。 相同的双字检测单元在第一管道上接收包括多个第一指令字段的第一指令和在第二管道上包括多个第二指令字段的第二指令。 相同的双字检测单元响应于第一指令字段和第二指令字段产生相同的双字信号。 高速缓存存储器从高速缓存存储器中的单个双字读取数据,并且响应于相同的双字信号同时向第一管道和第二管道提供双字。

    Performing a perform timing facility function instruction for synchronizing TOD clocks
    10.
    发明授权
    Performing a perform timing facility function instruction for synchronizing TOD clocks 有权
    执行用于同步TOD时钟的执行定时设备功能指令

    公开(公告)号:US08438415B2

    公开(公告)日:2013-05-07

    申请号:US13402554

    申请日:2012-02-22

    IPC分类号: G06F1/04 G04C11/00

    CPC分类号: G06F1/14

    摘要: A system, method and computer program product for steering a time-of-day (TOD) clock for a computer system having a physical clock providing a time base for executing operations that is stepped to a common oscillator. The method includes receiving, at a processing unit, a request to change a clock steering rate used to control a TOD-clock offset value for the processing unit, the TOD-clock offset defined as a function of a start time (s), a base offset (b), and a steering rate (r). The unit schedules a next episode start time with which to update the TOD-clock offset value. After updating TOD-clock offset value (d) at the scheduled time, TOD-clock offset value is added to a physical-clock value (Tr) value to obtain a logical TOD-clock value (Tb), where the logical TOD-clock value is adjustable without adjusting a stepping rate of the oscillator.

    摘要翻译: 一种用于转向具有物理时钟的计算机系统的时钟(TOD)时钟的系统,方法和计算机程序产品,该物理时钟提供用于执行步进到公共振荡器的操作的时基。 该方法包括在处理单元处接收用于改变用于控制处理单元的TOD时钟偏移值的时钟转向速率的请求,定义为开始时间的函数的TOD时钟偏移量, 基本偏移(b)和转向率(r)。 该单元安排下一个开始时间来更新TOD时钟偏移值。 在预定时间更新TOD时钟偏移值(d)后,将TOD时钟偏移值加到物理时钟值(Tr)值,以获得逻辑TOD时钟值(Tb),其中逻辑TOD时钟 值可调节,而不需要调整振荡器的步进速率。