公开(公告)号：US06653857B2

公开(公告)日：2003-11-25

申请号：US10000676

申请日：2001-10-31

Applicant: Sudhakar Bobba ,  Tyler Thorp

Inventor： Sudhakar Bobba ,  Tyler Thorp

IPC: H03K1716

CPC classification number: H04L25/08 ,  H01L23/5223 ,  H01L23/5225 ,  H01L23/5286 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit that asymmetrically shields a signal to increase decoupling capacitance is provided. The signal is asymmetrically shielded based on a probability of the signal being at a specific value. Further, a computer system that uses asymmetrically shielding to increase performance is provided. Further, a method for increasing an amount of implicit decoupling capacitance on a circuit through asymmetric shielding is provided. Further, a method to increase component performance by increasing implicit decoupling capacitance is provided.

Abstract translation: 提供了一种非对称屏蔽信号以增加去耦电容的集成电路。 基于信号处于特定值的概率，信号被不对称地屏蔽。 此外，提供了使用不对称屏蔽来提高性能的计算机系统。 此外，提供了一种通过非对称屏蔽增加电路上的隐式去耦电容量的方法。 此外，提供了通过增加隐式解耦电容来增加组件性能的方法。

公开(公告)号：US06640331B2

公开(公告)日：2003-10-28

申请号：US09997843

申请日：2001-11-29

Applicant: Pradeep Trivedi ,  Sudhakar Bobba ,  Tyler Thorp

Inventor： Pradeep Trivedi ,  Sudhakar Bobba ,  Tyler Thorp

IPC: G06F1750

CPC classification number: G06F17/5036

Abstract: A decoupling capacitor assignment technique that increases decoupling capacitance without violating a leakage power constraint of an integrated circuit is provided. The decoupling capacitor assignment technique selectively replaces decoupling capacitors associated with high driver decoupling capacitance need to available decoupling capacitance ratios with thin-oxide decoupling capacitors such that decoupling capacitance is increased and the leakage power constraint is met.

Abstract translation: 提供了一种在不违反集成电路的漏电功率限制的情况下增加去耦电容的去耦电容器分配技术。 去耦电容器分配技术选择性地替代与高驱动器去耦电容相关联的去耦电容需要使用薄氧化物去耦电容器的可用的去耦电容比，使得去耦电容增加并且满足泄漏功率约束。

公开(公告)号：US06566758B1

公开(公告)日：2003-05-20

申请号：US09995168

申请日：2001-11-27

Applicant: Pradeep Trivedi ,  Tyler Thorp ,  Sudhakar Bobba ,  Dean Liu

Inventor： Pradeep Trivedi ,  Tyler Thorp ,  Sudhakar Bobba ,  Dean Liu

IPC: H01L2348

CPC classification number: H01L24/10 ,  H01L23/5226 ,  H01L24/13 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00

Abstract: A current crowding reduction technique involving the uniform displacement of vias around a bump is provided. By uniformly arranging vias around the bump on an integrated circuit, current can uniformly flow to and from the bump, effectively leading to reduced current density around the bump. Further, a method for reducing current crowding around a bump using an uniform arrangement of vias around the bump is provided.

Abstract translation: 提供了一种包括围绕凸块的通孔均匀位移的当前拥挤减少技术。 通过在集成电路上的凸块周围均匀地布置通孔，电流可以均匀地流到凸起，从而有效地导致在凸块周围减小的电流密度。 此外，提供了一种用于使用凸块周围的通孔的均匀布置来减少在凸块周围的电流拥挤的方法。

公开(公告)号：US06658629B1

公开(公告)日：2003-12-02

申请号：US10142187

申请日：2002-05-09

Applicant: Sudhakar Bobba ,  Pradeep Trivedi ,  Tyler Thorp

Inventor： Sudhakar Bobba ,  Pradeep Trivedi ,  Tyler Thorp

IPC: G06F1750

CPC classification number: G06F17/5063 ,  G06F17/5036

Abstract: A technique for optimizing decoupling capacitance on an integrated circuit while meeting leakage power constraints of the integrated circuit is provided. The technique involves the formulation of a linear optimization problem using physical characteristics and constraints of the integrated circuit, where a linear solution to the linear optimization problem yields an optimal decoupling capacitance presence on the integrated circuit.

Abstract translation: 提供了一种在满足集成电路的漏电功率限制的情况下优化集成电路上的去耦电容的技术。 该技术涉及使用集成电路的物理特性和约束来制定线性优化问题，其中线性优化问题的线性解决方案在集成电路上产生最佳的去耦电容。

公开(公告)号：US06629306B2

公开(公告)日：2003-09-30

申请号：US09997918

申请日：2001-11-30

Applicant: Sudhakar Bobba ,  Tyler Thorp

Inventor： Sudhakar Bobba ,  Tyler Thorp

IPC: G06F1750

CPC classification number: H05K9/0039

Abstract: A method for preferentially shielding a signal to increase implicit decoupling capacitance is provided. The signal is preferentially shielded by using a probability of the signal being at a specific value to determine where to route the signal. Further, an integrated circuit that preferentially shields a signal to increase decoupling capacitance by 2using a probability of the signal being at a specific value to determine where to route the signal. Further, a computer system for preferentially shielding a signal to increase decoupling capacitance by using a probability of the signal being at a specific value to determine where to route the signal. Further, a computer readable medium having executable instructions for preferentially shielding a signal to increase implicit decoupling capacitance by using a probability of the signal being at a specific value to determine where to route the signal.

Abstract translation: 提供了一种优先屏蔽信号以增加隐式去耦电容的方法。 优先通过使用信号处于特定值的概率来确定信号来确定信号的路由。 此外，集成电路通过利用信号处于特定值的概率来确定信号路由位置优先屏蔽信号以增加去耦电容。 此外，一种用于通过使用信号处于特定值的概率来确定信号的路由来优先屏蔽信号以增加去耦电容的计算机系统。 此外，具有可执行指令的计算机可读介质，用于优先屏蔽信号以通过使用信号处于特定值的概率来确定在何处路由信号来增加隐式解耦电容。

公开(公告)号：US06495926B1

公开(公告)日：2002-12-17

申请号：US09997471

申请日：2001-11-29

Applicant: Sudhakar Bobba ,  Tyler Thorp ,  Dean Liu

Inventor： Sudhakar Bobba ,  Tyler Thorp ,  Dean Liu

IPC: H01L2348

CPC classification number: H01L24/17 ,  H01L23/50 ,  H01L23/5286 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/0401

Abstract: A 60 degree bump placement layout for an integrated circuit power grid is provided. This layout improves integrated circuit performance and reliability and gives an integrated circuit designer added flexibility and uniformity in designing the integrated circuit. Further, a patterned bump array for a top metal layer of an integrated circuit having a plurality of 60 degree bump placement structures is provided.

Abstract translation: 提供集成电路电网的60度凸块布置布局。 这种布局提高了集成电路的性能和可靠性，并为集成电路设计人员增加了设计集成电路的灵活性和均匀性。 此外，提供了具有多个60度凸块放置结构的集成电路的顶部金属层的图案化凸块阵列。

公开(公告)号：US06473883B1

公开(公告)日：2002-10-29

申请号：US09997437

申请日：2001-11-29

Applicant: Sudhakar Bobba ,  Tyler Thorp

Inventor： Sudhakar Bobba ,  Tyler Thorp

IPC: G06F1750

CPC classification number: G06F17/5068

Abstract: A method for improving integrated circuit by using a patterned bump layout on a layer of the integrated circuit is provided. The method creates various bump structures by varying an angle between a line from a reference bump to a first bump and a line from the reference bump to a second bump. By varying the angle, a designer may generate a particular bump structure that meets the needs of a particular design. Further, a particular bump placement may be repeated across all or a portion of the metal layer in order to create a patterned bump layout.

Abstract translation: 提供了一种通过在集成电路的层上使用图案化凸块布局来改善集成电路的方法。 该方法通过改变从参考凸起到第一凸起的线和从参考凸起到第二凸起的线之间的角度来产生各种凸起结构。 通过改变角度，设计者可以产生满足特定设计需要的特定凸起结构。 此外，可以在金属层的全部或一部分上重复特定的凸起布置，以便产生图案化的凸块布局。

公开(公告)号：US06971079B2

公开(公告)日：2005-11-29

申请号：US10245972

申请日：2002-09-18

Applicant: Gin Yee ,  Pradeep Trivedi ,  Sudhakar Bobba

Inventor： Gin Yee ,  Pradeep Trivedi ,  Sudhakar Bobba

IPC: G06F17/50 ,  G06F9/45

CPC classification number: G06F17/5031

Abstract: A method and apparatus for improving the timing accuracy of an integrated circuit through region-based voltage drop budgets is provided. Further, a method for performing timing analysis on an integrated circuit partitioned into voltage drop regions is provided. During the timing analysis, a set of logic paths segments in each voltage drop region is tested to ensure that the integrated circuit meets a set of predefined timing requirements. Logic path segments that reside in different voltage drop regions are tested using a supply voltage inputted by the respective voltage drop region.

Abstract translation: 提供了一种通过基于区域的电压降预算来提高集成电路的定时精度的方法和装置。 此外，提供了一种用于对分压成电压降区域的集成电路进行定时分析的方法。 在定时分析期间，测试每个压降区域中的一组逻辑路径段，以确保集成电路满足一组预定义的时序要求。 使用由各个电压降区域输入的电源电压来测试驻留在不同电压降区域中的逻辑路径段。

公开(公告)号：US06708314B2

公开(公告)日：2004-03-16

申请号：US10155149

申请日：2002-05-24

Applicant: Pradeep R. Trivedi ,  Sudhakar Bobba

Inventor： Pradeep R. Trivedi ,  Sudhakar Bobba

IPC: G06F1750

CPC classification number: G06F1/10 ,  G06F17/5077

Abstract: A technique that uses active shields to reduce clock skew is provided. The technique uses a shield wire for shielding the signal wire, a driver stage for driving a leading clock signal on the shielding wire, and a signal wire buffer for driving a lagging clock signal on the signal wire, where the leading clock signal is driven onto the first shield wire a phase difference before the lagging clock signal is driven onto the signal wire.

Abstract translation: 提供了一种使用主动屏蔽来减少时钟偏移的技术。 该技术使用屏蔽线来屏蔽信号线，用于驱动屏蔽线上的引导时钟信号的驱动级，以及用于驱动信号线上的滞后时钟信号的信号线缓冲器，其中引导时钟信号被驱动到 第一屏蔽线将滞后时钟信号之前的相位差驱动到信号线上。

公开(公告)号：US06784689B2

公开(公告)日：2004-08-31

申请号：US10068671

申请日：2002-02-06

Applicant: Sudhakar Bobba ,  Pradeep Trivedi

Inventor： Sudhakar Bobba ,  Pradeep Trivedi

IPC: H03K1716

CPC classification number: H04L25/242 ,  H03K5/12 ,  H03K19/01707

Abstract: A negative impedance device that accelerates signal transitions on a signal is provided. The negative impedance device is highly responsive to high to low and low to high transitions on the signal, and when one of these types of transitions begins to occur on the signal, the negative impedance device senses the transition and quickly drives the signal to the intended value before a point in time when the signal would have reached the intended value had the negative impedance device not been used. Further, a signal transition accelerator design that reduces signal rise and fall times is provided. Further, a method for accelerating a signal transition is provided.

Abstract translation: 提供加速信号上的信号转换的负阻抗器件。 负阻抗器件对信号的高到低和低到高的转变都是高度响应的，并且当这些类型的转换之一在信号上开始发生时，负阻抗器件感测到转换并且迅速地将信号驱动到预期 在信号将达到预期值的时间点之前的值未被使用的负阻抗器件。 此外，提供了降低信号上升和下降时间的信号转换加速器设计。 此外，提供了一种加速信号转换的方法。