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48 条记录 (耗时 0.03 秒)

    Decoupling capacitor assignment technique with respect to leakage power
    3.
    发明授权
    Decoupling capacitor assignment technique with respect to leakage power 有权
    去耦电容器分配技术相对漏电功率

    公开(公告)号：US06640331B2

    公开(公告)日：2003-10-28

    申请号：US09997843

    申请日：2001-11-29

    申请人： Pradeep Trivedi ,  Sudhakar Bobba ,  Tyler Thorp

    发明人： Pradeep Trivedi ,  Sudhakar Bobba ,  Tyler Thorp

    IPC分类号： G06F1750

    CPC分类号： G06F17/5036

    摘要： A decoupling capacitor assignment technique that increases decoupling capacitance without violating a leakage power constraint of an integrated circuit is provided. The decoupling capacitor assignment technique selectively replaces decoupling capacitors associated with high driver decoupling capacitance need to available decoupling capacitance ratios with thin-oxide decoupling capacitors such that decoupling capacitance is increased and the leakage power constraint is met.

    摘要翻译： 提供了一种在不违反集成电路的漏电功率限制的情况下增加去耦电容的去耦电容器分配技术。 去耦电容器分配技术选择性地替代与高驱动器去耦电容相关联的去耦电容需要使用薄氧化物去耦电容器的可用的去耦电容比，使得去耦电容增加并且满足泄漏功率约束。

    Technique for optimizing decoupling capacitance subject to leakage power constraints
    5.
    发明授权
    Technique for optimizing decoupling capacitance subject to leakage power constraints 有权
    用于优化去耦电容受漏电功率限制的技术

    公开(公告)号：US06658629B1

    公开(公告)日：2003-12-02

    申请号：US10142187

    申请日：2002-05-09

    申请人： Sudhakar Bobba ,  Pradeep Trivedi ,  Tyler Thorp

    发明人： Sudhakar Bobba ,  Pradeep Trivedi ,  Tyler Thorp

    IPC分类号： G06F1750

    CPC分类号： G06F17/5063 ,  G06F17/5036

    摘要： A technique for optimizing decoupling capacitance on an integrated circuit while meeting leakage power constraints of the integrated circuit is provided. The technique involves the formulation of a linear optimization problem using physical characteristics and constraints of the integrated circuit, where a linear solution to the linear optimization problem yields an optimal decoupling capacitance presence on the integrated circuit.

    摘要翻译： 提供了一种在满足集成电路的漏电功率限制的情况下优化集成电路上的去耦电容的技术。 该技术涉及使用集成电路的物理特性和约束来制定线性优化问题，其中线性优化问题的线性解决方案在集成电路上产生最佳的去耦电容。

    Accuracy of timing analysis using region-based voltage drop budgets
    6.
    发明授权
    Accuracy of timing analysis using region-based voltage drop budgets 有权
    使用基于区域的电压降预算的时序分析的准确性

    公开(公告)号：US06971079B2

    公开(公告)日：2005-11-29

    申请号：US10245972

    申请日：2002-09-18

    申请人： Gin Yee ,  Pradeep Trivedi ,  Sudhakar Bobba

    发明人： Gin Yee ,  Pradeep Trivedi ,  Sudhakar Bobba

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5031

    摘要： A method and apparatus for improving the timing accuracy of an integrated circuit through region-based voltage drop budgets is provided. Further, a method for performing timing analysis on an integrated circuit partitioned into voltage drop regions is provided. During the timing analysis, a set of logic paths segments in each voltage drop region is tested to ensure that the integrated circuit meets a set of predefined timing requirements. Logic path segments that reside in different voltage drop regions are tested using a supply voltage inputted by the respective voltage drop region.

    摘要翻译： 提供了一种通过基于区域的电压降预算来提高集成电路的定时精度的方法和装置。 此外，提供了一种用于对分压成电压降区域的集成电路进行定时分析的方法。 在定时分析期间，测试每个压降区域中的一组逻辑路径段，以确保集成电路满足一组预定义的时序要求。 使用由各个电压降区域输入的电源电压来测试驻留在不同电压降区域中的逻辑路径段。

    Transmission gate based signal transition accelerator
    7.
    发明授权
    Transmission gate based signal transition accelerator 有权
    基于传输门限的信号转换加速器

    公开(公告)号：US06784689B2

    公开(公告)日：2004-08-31

    申请号：US10068671

    申请日：2002-02-06

    申请人： Sudhakar Bobba ,  Pradeep Trivedi

    发明人： Sudhakar Bobba ,  Pradeep Trivedi

    IPC分类号： H03K1716

    CPC分类号： H04L25/242 ,  H03K5/12 ,  H03K19/01707

    摘要： A negative impedance device that accelerates signal transitions on a signal is provided. The negative impedance device is highly responsive to high to low and low to high transitions on the signal, and when one of these types of transitions begins to occur on the signal, the negative impedance device senses the transition and quickly drives the signal to the intended value before a point in time when the signal would have reached the intended value had the negative impedance device not been used. Further, a signal transition accelerator design that reduces signal rise and fall times is provided. Further, a method for accelerating a signal transition is provided.

    摘要翻译： 提供加速信号上的信号转换的负阻抗器件。 负阻抗器件对信号的高到低和低到高的转变都是高度响应的，并且当这些类型的转换之一在信号上开始发生时，负阻抗器件感测到转换并且迅速地将信号驱动到预期 在信号将达到预期值的时间点之前的值未被使用的负阻抗器件。 此外，提供了降低信号上升和下降时间的信号转换加速器设计。 此外，提供了一种加速信号转换的方法。

    Dynamic modulation of on-chip supply voltage for low-power design
    8.
    发明授权
    Dynamic modulation of on-chip supply voltage for low-power design 有权
    低功耗设计的片上电源动态调制

    公开(公告)号：US06737844B2

    公开(公告)日：2004-05-18

    申请号：US10156583

    申请日：2002-05-28

    申请人： Pradeep Trivedi ,  Sudhakar Bobba

    发明人： Pradeep Trivedi ,  Sudhakar Bobba

    IPC分类号： G05F1565

    CPC分类号： G11C5/147

    摘要： A modulation circuit arranged to modulate a first voltage from a first power supply grid to produce a desired second voltage not greater than the first voltage on a second power supply grid is provided. A digital register is operatively connected to the modulation circuit to determine the desired second voltage on the second power supply grid. Furthermore, the digital register maintains a value representative of an activity level or an anticipated activity level of a circuit connected to the second power supply grid. The modulation circuit maintains the desired second voltage for the circuit connected to the second power supply grid by transferring charge between capacitances.

    摘要翻译： 一种调制电路，被配置为调制来自第一电源电网的第一电压以产生不大于第二电源网格上的第一电压的期望的第二电压。 数字寄存器可操作地连接到调制电路以确定第二电源电网上的期望的第二电压。 此外，数字寄存器保持代表连接到第二电源网格的电路的活动水平或预期活动水平的值。 调制电路通过在电容之间传送电荷来维持连接到第二电源电网的电路的期望的第二电压。

    Multiple supply voltage dynamic logic
    9.
    发明授权
    Multiple supply voltage dynamic logic 有权
    多电源电压动态逻辑

    公开(公告)号：US06646473B1

    公开(公告)日：2003-11-11

    申请号：US10170845

    申请日：2002-06-13

    申请人： Pradeep Trivedi ,  Sudhakar Bobba

    发明人： Pradeep Trivedi ,  Sudhakar Bobba

    IPC分类号： H03K19096

    CPC分类号： H03K19/0963 ,  H03K19/0016

    摘要： A dynamic circuit capable of operating in a normal power consumption mode and at least one reduced power consumption mode is provided. The dynamic circuit is operatively connected to a normal supply voltage and a reduced supply voltage, and is capable of operating at either the normal supply voltage and a normal frequency or at the reduced supply voltage and a reduced frequency. By using such a dynamic circuit, power consumption may be selectively controlled in order to reduce unnecessary power consumption.

    摘要翻译： 提供能够以正常功耗模式和至少一个降低的功耗模式操作的动态电路。 动态电路可操作地连接到正常电源电压和降低的电源电压，并且能够在正常电源电压和正常频率或降低的电源电压和降低的频率下操作。 通过使用这样的动态电路，可以选择性地控制功率消耗，以便减少不必要的功耗。

    Clock power reduction technique using multi-level voltage input clock driver
    10.
    发明授权
    Clock power reduction technique using multi-level voltage input clock driver 有权
    时钟功率降低技术采用多电平电压输入时钟驱动

    公开(公告)号：US06646472B1

    公开(公告)日：2003-11-11

    申请号：US10156249

    申请日：2002-05-28

    申请人： Pradeep Trivedi ,  Sudhakar Bobba

    发明人： Pradeep Trivedi ,  Sudhakar Bobba

    IPC分类号： H03K1900

    CPC分类号： G06F1/10 ,  G06F1/3203

    摘要： A technique for reducing the power consumed by a clock driver circuit involves selecting between a first power supply path and a second power supply path in response to a power reduction signal. A driver circuit drives an output clock signal from the selected one of the first power supply path and the second power supply path. By reducing the voltage on one of the first power supply path and the second power supply path, the power consumed by the clock driver circuit may be selectively reduced.

    摘要翻译： 用于减少时钟驱动器电路消耗的功率的技术包括响应于功率降低信号在第一电源路径和第二电源路径之间进行选择。 驱动电路驱动来自第一电源路径和第二电源路径中选择的一个的输出时钟信号。 通过降低第一电源路径和第二电源路径中的一个电压，可以选择性地减少由时钟驱动器电路消耗的功率。