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    Accuracy of timing analysis using region-based voltage drop budgets
    1.
    发明授权
    Accuracy of timing analysis using region-based voltage drop budgets 有权
    使用基于区域的电压降预算的时序分析的准确性

    公开(公告)号：US06971079B2

    公开(公告)日：2005-11-29

    申请号：US10245972

    申请日：2002-09-18

    Applicant: Gin Yee ,  Pradeep Trivedi ,  Sudhakar Bobba

    Inventor： Gin Yee ,  Pradeep Trivedi ,  Sudhakar Bobba

    IPC: G06F17/50 ,  G06F9/45

    CPC classification number: G06F17/5031

    Abstract: A method and apparatus for improving the timing accuracy of an integrated circuit through region-based voltage drop budgets is provided. Further, a method for performing timing analysis on an integrated circuit partitioned into voltage drop regions is provided. During the timing analysis, a set of logic paths segments in each voltage drop region is tested to ensure that the integrated circuit meets a set of predefined timing requirements. Logic path segments that reside in different voltage drop regions are tested using a supply voltage inputted by the respective voltage drop region.

    Abstract translation: 提供了一种通过基于区域的电压降预算来提高集成电路的定时精度的方法和装置。 此外，提供了一种用于对分压成电压降区域的集成电路进行定时分析的方法。 在定时分析期间，测试每个压降区域中的一组逻辑路径段，以确保集成电路满足一组预定义的时序要求。 使用由各个电压降区域输入的电源电压来测试驻留在不同电压降区域中的逻辑路径段。

    Transmission gate based signal transition accelerator
    2.
    发明授权
    Transmission gate based signal transition accelerator 有权
    基于传输门限的信号转换加速器

    公开(公告)号：US06784689B2

    公开(公告)日：2004-08-31

    申请号：US10068671

    申请日：2002-02-06

    Applicant: Sudhakar Bobba ,  Pradeep Trivedi

    Inventor： Sudhakar Bobba ,  Pradeep Trivedi

    IPC: H03K1716

    CPC classification number: H04L25/242 ,  H03K5/12 ,  H03K19/01707

    Abstract: A negative impedance device that accelerates signal transitions on a signal is provided. The negative impedance device is highly responsive to high to low and low to high transitions on the signal, and when one of these types of transitions begins to occur on the signal, the negative impedance device senses the transition and quickly drives the signal to the intended value before a point in time when the signal would have reached the intended value had the negative impedance device not been used. Further, a signal transition accelerator design that reduces signal rise and fall times is provided. Further, a method for accelerating a signal transition is provided.

    Abstract translation: 提供加速信号上的信号转换的负阻抗器件。 负阻抗器件对信号的高到低和低到高的转变都是高度响应的，并且当这些类型的转换之一在信号上开始发生时，负阻抗器件感测到转换并且迅速地将信号驱动到预期 在信号将达到预期值的时间点之前的值未被使用的负阻抗器件。 此外，提供了降低信号上升和下降时间的信号转换加速器设计。 此外，提供了一种加速信号转换的方法。

    Dynamic modulation of on-chip supply voltage for low-power design
    3.
    发明授权
    Dynamic modulation of on-chip supply voltage for low-power design 有权
    低功耗设计的片上电源动态调制

    公开(公告)号：US06737844B2

    公开(公告)日：2004-05-18

    申请号：US10156583

    申请日：2002-05-28

    Applicant: Pradeep Trivedi ,  Sudhakar Bobba

    Inventor： Pradeep Trivedi ,  Sudhakar Bobba

    IPC: G05F1565

    CPC classification number: G11C5/147

    Abstract: A modulation circuit arranged to modulate a first voltage from a first power supply grid to produce a desired second voltage not greater than the first voltage on a second power supply grid is provided. A digital register is operatively connected to the modulation circuit to determine the desired second voltage on the second power supply grid. Furthermore, the digital register maintains a value representative of an activity level or an anticipated activity level of a circuit connected to the second power supply grid. The modulation circuit maintains the desired second voltage for the circuit connected to the second power supply grid by transferring charge between capacitances.

    Abstract translation: 一种调制电路，被配置为调制来自第一电源电网的第一电压以产生不大于第二电源网格上的第一电压的期望的第二电压。 数字寄存器可操作地连接到调制电路以确定第二电源电网上的期望的第二电压。 此外，数字寄存器保持代表连接到第二电源网格的电路的活动水平或预期活动水平的值。 调制电路通过在电容之间传送电荷来维持连接到第二电源电网的电路的期望的第二电压。

    Multiple supply voltage dynamic logic
    4.
    发明授权
    Multiple supply voltage dynamic logic 有权
    多电源电压动态逻辑

    公开(公告)号：US06646473B1

    公开(公告)日：2003-11-11

    申请号：US10170845

    申请日：2002-06-13

    Applicant: Pradeep Trivedi ,  Sudhakar Bobba

    Inventor： Pradeep Trivedi ,  Sudhakar Bobba

    IPC: H03K19096

    CPC classification number: H03K19/0963 ,  H03K19/0016

    Abstract: A dynamic circuit capable of operating in a normal power consumption mode and at least one reduced power consumption mode is provided. The dynamic circuit is operatively connected to a normal supply voltage and a reduced supply voltage, and is capable of operating at either the normal supply voltage and a normal frequency or at the reduced supply voltage and a reduced frequency. By using such a dynamic circuit, power consumption may be selectively controlled in order to reduce unnecessary power consumption.

    Abstract translation: 提供能够以正常功耗模式和至少一个降低的功耗模式操作的动态电路。 动态电路可操作地连接到正常电源电压和降低的电源电压，并且能够在正常电源电压和正常频率或降低的电源电压和降低的频率下操作。 通过使用这样的动态电路，可以选择性地控制功率消耗，以便减少不必要的功耗。

    Phase locked loop design with diode for loop filter capacitance leakage current control
    6.
    发明授权
    Phase locked loop design with diode for loop filter capacitance leakage current control 有权
    具有二极管的锁相环设计，用于环路滤波器电容漏电流控制

    公开(公告)号：US06861885B2

    公开(公告)日：2005-03-01

    申请号：US10199426

    申请日：2002-07-19

    Applicant: Pradeep Trivedi ,  Sudhakar Bobba ,  Claude Gauthier

    Inventor： Pradeep Trivedi ,  Sudhakar Bobba ,  Claude Gauthier

    IPC: H03L7/089 ,  H03L7/093 ,  H03L7/06

    CPC classification number: H03L7/093 ,  H03L7/0891 ,  Y10S331/02

    Abstract: A phase locked loop design uses a diode operatively connected to a loop filter capacitor to control a leakage current of the loop filter capacitor. By positioning a diode in series with the loop filter capacitor, a voltage potential across the loop filter capacitor is reduced, thereby reducing the leakage current of the loop filter capacitor. Moreover, the leakage current of the loop filter capacitor is controlled in that it cannot exceed the current through the diode. Control and reduction of the loop filter capacitor leakage current leads to more reliable and stable phase locked loop behavior.

    Abstract translation: 锁相环设计使用可操作地连接到环路滤波电容器的二极管来控制环路滤波电容器的漏电流。 通过与环路滤波电容串联定位二极管，减小环路滤波电容两端的电压电位，从而减小环路滤波电容的漏电流。 此外，环路滤波电容器的漏电流被控制为不能超过二极管的电流。 控制和减少环路滤波电容器的漏电流导致更可靠和稳定的锁相环行为。

    Frequency multiplier design
    8.
    发明授权
    Frequency multiplier design 有权
    倍频器设计

    公开(公告)号：US06642756B1

    公开(公告)日：2003-11-04

    申请号：US10202798

    申请日：2002-07-25

    Applicant: Gin Yee ,  Sudhakar Bobba ,  Lynn Ooi ,  Pradeep Trivedi

    Inventor： Gin Yee ,  Sudhakar Bobba ,  Lynn Ooi ,  Pradeep Trivedi

    IPC: H03B1900

    CPC classification number: G06F7/68 ,  H03K5/00006

    Abstract: A frequency multiplier design that uses a flip-flop to output (1) a first edge on an output clock signal upon receipt of a first transition of an input clock signal and (2) a second edge on the output clock signal before receipt of a second transition of the input clock signal is provided. The frequency multiplier design uses circuitry dependent on the output clock signal to reset the flip-flop after some delay but before the second transition of the input clock signal, wherein the resetting of the flip-flop causes the flip-flop to output the second edge on the output clock signal.

    Abstract translation: 一种倍增器设计，其使用触发器在接收到输入时钟信号的第一转换时输出（1）输出时钟信号上的第一边沿，以及（2）在接收到输出时钟信号之前的输出时钟信号上的第二边沿 提供输入时钟信号的第二转换。 倍频器设计使用取决于输出时钟信号的电路，在一段延迟之后但在输入时钟信号的第二次转换之前复位触发器，其中触发器的复位使触发器输出第二边沿 对输出时钟信号。

    Decoupling capacitor assignment technique with respect to leakage power
    9.
    发明授权
    Decoupling capacitor assignment technique with respect to leakage power 有权
    去耦电容器分配技术相对漏电功率

    公开(公告)号：US06640331B2

    公开(公告)日：2003-10-28

    申请号：US09997843

    申请日：2001-11-29

    Applicant: Pradeep Trivedi ,  Sudhakar Bobba ,  Tyler Thorp

    Inventor： Pradeep Trivedi ,  Sudhakar Bobba ,  Tyler Thorp

    IPC: G06F1750

    CPC classification number: G06F17/5036

    Abstract: A decoupling capacitor assignment technique that increases decoupling capacitance without violating a leakage power constraint of an integrated circuit is provided. The decoupling capacitor assignment technique selectively replaces decoupling capacitors associated with high driver decoupling capacitance need to available decoupling capacitance ratios with thin-oxide decoupling capacitors such that decoupling capacitance is increased and the leakage power constraint is met.

    Abstract translation: 提供了一种在不违反集成电路的漏电功率限制的情况下增加去耦电容的去耦电容器分配技术。 去耦电容器分配技术选择性地替代与高驱动器去耦电容相关联的去耦电容需要使用薄氧化物去耦电容器的可用的去耦电容比，使得去耦电容增加并且满足泄漏功率约束。

    Sliding grid based technique for optimal on-chip decap insertion
    10.
    发明授权
    Sliding grid based technique for optimal on-chip decap insertion 有权
    基于滑动网格的技术，可实现最佳片上分拆插入

    公开(公告)号：US06625791B1

    公开(公告)日：2003-09-23

    申请号：US10143067

    申请日：2002-05-10

    Applicant: Sudhakar Bobba ,  Pradeep Trivedi

    Inventor： Sudhakar Bobba ,  Pradeep Trivedi

    IPC: G06F945

    CPC classification number: G06F17/5068

    Abstract: A method and apparatus for optimizing the insertion of decoupling capacitance onto an integrated circuit is provided. Further, a sliding grid based technique for arraying decoupling capacitors into a white-space of an integrated includes sliding a bounded grid across the white-space in order to determine an optimal decap insertion for the white-space. The bounded grid is slid across the white-space in discrete steps. At each discrete step, a potential decap layout is calculated for the region of the white-space that intersects the bounded grid. After a set of potential decap layouts have been calculated for the white-space, the potential decap layout that yields optimal decap insertion is selected, and decap cells are arrayed into the area(s) of the white-space that are demarcated by the selected decap layout.

    Abstract translation: 提供了一种用于优化将去耦电容插入集成电路的方法和装置。 此外，用于将去耦电容器排列到集成的白色空间中的基于滑动网格的技术包括在白色空间上滑动有界网格，以便确定白色空间的最佳切片插入。 有界网格以离散步骤滑过白色空间。 在每个离散步骤中，对于与有界网格相交的白色空间的区域计算潜在的拆分布局。 在为白色空间计算了一组潜在的拆分布局之后，选择产生最佳拆包插入的潜在的拆分布局，并将拆分单元排列到由所选择的边界划分的空白区域中 拆分布局。

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