公开(公告)号：US20170195900A1

公开(公告)日：2017-07-06

申请号：US15398617

申请日：2017-01-04

申请人： Mehran Nekuii ,  Frank Henry Worrell ,  Hong Jik Kim

发明人： Mehran Nekuii ,  Frank Henry Worrell ,  Hong Jik Kim

IPC分类号： H04W24/02 ,  H04W72/04

CPC分类号： H04W24/02 ,  H04W88/08

摘要： Methods and apparatus for configuring a front end to process multiple sectors with multiple radio frequency frames. In an exemplary embodiment, a method includes decoding instructions included in a job description list, and configuring one or more processing functions of a transceiver to process a radio signal associated with a selected sector based on the decoded instructions. The configuration of the processing functions is synchronized according to time control instructions included in the job description list.

公开(公告)号：US20170195281A1

公开(公告)日：2017-07-06

申请号：US15347663

申请日：2016-11-09

申请人： Yuanbin Guo ,  Hong Jik Kim

发明人： Yuanbin Guo ,  Hong Jik Kim

IPC分类号： H04L29/12 ,  H04L27/26 ,  H04L29/06 ,  G06F17/14 ,  H04W4/00

CPC分类号： H04W4/80 ,  G06F17/142 ,  H04L27/2636

摘要： Twiddle factor generation for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes look-up table logic that receives twiddle control factors and outputs a selected twiddle factor scaler value (TFSV), a base vector generator that generates a base vector values based on the selected TFSV, and a twiddle column generator that generates a twiddle vector from the base vector.

公开(公告)号：US20190021013A1

公开(公告)日：2019-01-17

申请号：US15693020

申请日：2017-08-31

申请人： Ahmed Shahid ,  Jason Daniel Zebchuk ,  Tejas Maheshbhai Bhatt ,  Hong Jik Kim

发明人： Ahmed Shahid ,  Jason Daniel Zebchuk ,  Tejas Maheshbhai Bhatt ,  Hong Jik Kim

IPC分类号： H04W24/02 ,  H04L5/00 ,  H04B7/024 ,  H04W72/12 ,  H04L12/26 ,  H04L25/02

CPC分类号： H04W24/02 ,  H04B7/024 ,  H04B7/0837 ,  H04L5/0035 ,  H04L25/02 ,  H04L43/0852 ,  H04W72/12 ,  H04W72/1289 ,  H04W88/02 ,  H04W88/085

摘要： Methods and apparatus for coordinated multipoint receiver processing acceleration and latency reduction. In an exemplary embodiment, an apparatus includes a receiver that receives symbols from a wireless transmission and stores the symbols in a memory. The receiver also outputs an indicator that indicates that storage of the symbols in the memory has begun. The apparatus also includes a controller that outputs control signaling in response to the indicator. The apparatus also includes a link that acquires the symbols and remote scheduling and control information (RSCI) from the memory in response to receiving the control signaling. The link combines the symbols with the RSCI to form packets and transmits the packets to an external system.

公开(公告)号：US10140250B2

公开(公告)日：2018-11-27

申请号：US15379207

申请日：2016-12-14

申请人： Mehran Nekuii ,  Hong Jik Kim

发明人： Mehran Nekuii ,  Hong Jik Kim

IPC分类号： G06F17/14 ,  H04J11/00

摘要： Methods and apparatus for providing an FFT engine using a reconfigurable single delay feedback architecture. In one aspect, an apparatus includes a radix-2 (R2) single delay feedback (SDF) stage that generates a radix-2 output and a radix-3 (R3) SDF stage that generates a radix-3 output. The apparatus also includes one or more radix-2 squared (R2^2) SDF stages that generate a radix-4 output. The apparatus further includes a controller that configures a sequence of radix stages selected from the R2, R3, and R2^2 stages based on an FFT point size to form an FFT engine. The FFT engine receives input samples at a first stage of the sequence and generate an FFT output result that is output from a last stage of the sequence. The sequence includes no more than one R3 stage.

公开(公告)号：US20170192935A1

公开(公告)日：2017-07-06

申请号：US15292015

申请日：2016-10-12

申请人： Yuanbin Guo ,  Hong Jik Kim

发明人： Yuanbin Guo ,  Hong Jik Kim

IPC分类号： G06F15/80 ,  G06F9/30 ,  G06F17/14

CPC分类号： G06F15/8061 ,  G06F9/30036 ,  G06F17/141 ,  G06F17/142

摘要： A vector memory subsystem for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes a vector memory bank and a vector memory system (VMS) that generates input memory addresses that are used to store input data into the vector memory bank. The VMS also generates output memory addresses that are used to unload vector data from the memory banks. The input memory addresses are used to shuffle the input data in the memory bank based on a radix factorization associated with an N-point DFT, and the output memory addresses are used to unload the vector data from the memory bank to compute radix factors of the radix factorization.

公开(公告)号：US20170170930A1

公开(公告)日：2017-06-15

申请号：US15378750

申请日：2016-12-14

申请人： Sabih Guzelgoz ,  Hong Jik Kim ,  Tejas Maheshbhai Bhatt ,  Fariba Heidari

发明人： Sabih Guzelgoz ,  Hong Jik Kim ,  Tejas Maheshbhai Bhatt ,  Fariba Heidari

IPC分类号： H04L1/16 ,  H04W72/12 ,  H04L5/00

CPC分类号： H04L5/0055 ,  H04L1/0026 ,  H04L1/0035 ,  H04L1/1664 ,  H04L5/0057 ,  H04L25/067 ,  H04W72/121 ,  H04W72/1268

摘要： Methods and apparatus for providing soft and blind combining for PUSCH acknowledgement (ACK) processing. In an exemplary embodiment, a method includes soft-combining acknowledgement (ACK) bits received from a UE that are contained in a received sub-frame of symbols. The ACK bits are soft-combined using a plurality of scrambling sequences to generate a plurality of hypothetical soft-combined ACK bit streams. The method also includes receiving a parameter that identifies a selected scrambling sequence to be used. The method also includes decoding a selected hypothetical soft-combined ACK bit stream to generate a decoded ACK value, wherein the selected hypothetical soft-combined ACK bit stream is selected from the plurality of hypothetical soft-combined ACK bit streams based on the parameter.