公开(公告)号：US08552587B2

公开(公告)日：2013-10-08

申请号：US12840130

申请日：2010-07-20

Applicant: Sunit Tyagi ,  Hemanshu Bhatt

Inventor： Sunit Tyagi ,  Hemanshu Bhatt

IPC: H02J1/10

CPC classification number: H02M7/537 ,  H02J3/383 ,  H02M7/493 ,  H02M2007/4815 ,  Y02B70/1441 ,  Y02E10/563 ,  Y10T307/50 ,  Y10T307/658 ,  Y10T307/713

Abstract: Embodiments related to the conversion of DC power to AC power are disclosed. For example, one disclosed embodiment provides a power conversion system, comprising a plurality of direct current (DC) power sources, a plurality of power output circuits connected to one another in a parallel arrangement, each power output circuit being connected to a corresponding DC power source to receive power from the corresponding DC power source and to selectively discharge power received from the corresponding DC power source, a power combiner configured to combine power received from the plurality of power output circuits to form a combined power signal, an output stage configured to convert the combined power signal into an AC signal or a DC signal, and a controller in electrical communication with each power outlet circuit and the power combiner to control the output of power by the power converter.

Abstract translation: 公开了将直流电转换为交流电力的实施例。 例如，一个公开的实施例提供了一种功率转换系统，其包括多个直流（DC）电源，多个以并联装置彼此连接的功率输出电路，每个功率输出电路连接到相应的直流电力 源极，用于从相应的直流电源接收电力并选择性地放电从相应的直流电源接收的功率;功率组合器，被配置为组合从多个功率输出电路接收的功率以形成组合的功率信号;输出级，被配置为 将组合的功率信号转换为AC信号或DC信号，以及与每个电源插座电路和功率组合器电连接的控制器，以通过功率转换器来控制功率的输出。

公开(公告)号：US20070132034A1

公开(公告)日：2007-06-14

申请号：US11304016

申请日：2005-12-14

Applicant: Giuseppe Curello ,  Mark Bohr ,  Hemant Deshpande ,  Sunit Tyagi

Inventor： Giuseppe Curello ,  Mark Bohr ,  Hemant Deshpande ,  Sunit Tyagi

IPC: H01L29/76

CPC classification number: H01L21/823481 ,  H01L21/76232 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor device and method for its fabrication are described. An isolation body may be formed prior to formation of an active region. In one embodiment, the isolation body is void-free.

Abstract translation: 对半导体装置及其制造方法进行说明。 可以在形成活性区域之前形成隔离体。 在一个实施例中，隔离体是无空隙的。

公开(公告)号：US20070022360A1

公开(公告)日：2007-01-25

申请号：US11174003

申请日：2005-06-30

Applicant: Nivruti Rai ,  Anshumali Kumar ,  Edward Burton ,  Sunit Tyagi ,  Jeffrey Miller

Inventor： Nivruti Rai ,  Anshumali Kumar ,  Edward Burton ,  Sunit Tyagi ,  Jeffrey Miller

IPC: G11C29/00

CPC classification number: G11C11/417

Abstract: A method comprising running an error correction code on data and storing the data and the result of the error correction code in memory, running an error correction code on the data when it is read from the memory, comparing the results of the error correction codes on the data from before and after the memory, correcting errors when the comparator determines a difference in the results of the error correction codes and lowering the operating voltage of the memory array while using the error correction.

Abstract translation: 一种方法，包括在数据上运行纠错码并将数据和纠错码的结果存储在存储器中，当从存储器读取数据时对数据进行纠错码，将纠错码的结果与 来自存储器之前和之后的数据，当比较器确定误差校正码的结果的差异并且在使用纠错时降低存储器阵列的工作电压时校正错误。

公开(公告)号：US20060084216A1

公开(公告)日：2006-04-20

申请号：US11292428

申请日：2005-12-01

Applicant: Stephen Cea ,  Ravindra Soman ,  Ramune Nagisetty ,  Sunit Tyagi ,  Sanjay Natarajan

Inventor： Stephen Cea ,  Ravindra Soman ,  Ramune Nagisetty ,  Sunit Tyagi ,  Sanjay Natarajan

IPC: H01L21/8234

CPC classification number: H01L29/66636 ,  H01L29/1054 ,  H01L29/7842

Abstract: Various methods for forming a layer of strained silicon in a channel region of a device and devices constructed according to the disclosed methods. In one embodiment, a strain-inducing layer is formed, a relaxed layer is formed on the strain-inducing layer, a portion of the strain-inducing layer is removed, which allows the strain-inducing layer to relax and strain the relaxed layer.

公开(公告)号：US07019326B2

公开(公告)日：2006-03-28

申请号：US10714139

申请日：2003-11-14

Applicant: Stephen M. Cea ,  Ravindra Soman ,  Ramune Nagisetty ,  Sunit Tyagi ,  Sanjay Natarajan

Inventor： Stephen M. Cea ,  Ravindra Soman ,  Ramune Nagisetty ,  Sunit Tyagi ,  Sanjay Natarajan

IPC: H01L29/06

CPC classification number: H01L29/66636 ,  H01L29/1054 ,  H01L29/7842

Abstract: Various methods for forming a layer of strained silicon in a channel region of a device and devices constructed according to the disclosed methods. In one embodiment, a strain-inducing layer is formed, a relaxed layer is formed on the strain-inducing layer, a portion of the strain-inducing layer is removed, which allows the strain-inducing layer to relax and strain the relaxed layer.

公开(公告)号：US06458667B1

公开(公告)日：2002-10-01

申请号：US09531805

申请日：2000-03-21

Applicant: Sunit Tyagi ,  Shahriar S. Ahmed

Inventor： Sunit Tyagi ,  Shahriar S. Ahmed

IPC: H01L21336

CPC classification number: H01L29/7393

Abstract: An improved MOS transistor and method for making it are described. The MOS transistor's source and drain have a first conductivity type and are separated from each other by a first region having a second conductivity type opposite to the first conductivity type. A second region, also having the second conductivity type, is formed adjacent to the drain and is separated from the first region by the drain.

Abstract translation: 描述了一种改进的MOS晶体管及其制造方法。 MOS晶体管的源极和漏极具有第一导电类型，并且通过具有与第一导电类型相反的第二导电类型的第一区域彼此分离。 还具有第二导电类型的第二区域邻近漏极形成，并且通过漏极与第一区域分离。

公开(公告)号：US06297104B1

公开(公告)日：2001-10-02

申请号：US09496833

申请日：2000-02-02

Applicant: Sunit Tyagi ,  Shahriar S. Ahmed

Inventor： Sunit Tyagi ,  Shahriar S. Ahmed

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L29/66659 ,  H01L29/7835

Abstract: Metal Oxide Semiconductor Field Effect Transistors (MOSFET) are disclosed. One MOSFET includes, a substrate having a well of a first conductivity type. The MOSFET also includes source and drain regions, of a second conductivity type, formed in the well arranged apart from each other. Moreover, the MOSFET includes a first region, of a second conductivity type, formed in the well near the drain region. The first region has a low doping. Furthermore, the MOSFET includes a second region of a second conductivity type, formed near the source region. The second region has a doping substantially higher than the doping of the first region. A second MOSFET includes a substrate having a well of a first conductivity type and source and drain regions, of a second conductivity type, formed in the well apart from each other. Moreover, the MOSFET includes a drain extension region of the second conductivity type, formed in the well near the drain region. Furthermore, the MOSFET includes a source extension region, of the second conductivity type, formed in the well near the source region. The source extension region is doped more heavily than the drain extension region. The source extension region extends deeper in the well than the drain extension region.

Abstract translation: 公开了金属氧化物半导体场效应晶体管（MOSFET）。 一个MOSFET包括具有第一导电类型的阱的衬底。 MOSFET还包括第二导电类型的源极和漏极区域，其形成在彼此分开布置的阱中。 此外，MOSFET包括形成在漏区附近的阱中的第二导电类型的第一区域。 第一个区域掺杂低。 此外，MOSFET包括在源极区附近形成的第二导电类型的第二区域。 第二区域具有比第一区域的掺杂显着更高的掺杂。 第二MOSFET包括具有第一导电类型的阱以及形成在彼此远离的第二导电类型的源极和漏极区的衬底。 此外，MOSFET包括形成在漏极区附近的阱中的第二导电类型的漏极延伸区域。 此外，MOSFET包括形成在源区附近的阱中的第二导电类型的源极延伸区域。 源极延伸区域比漏极延伸区域更重掺杂。 源极延伸区域在阱中比漏极延伸区域更深。

公开(公告)号：US06200879B1

公开(公告)日：2001-03-13

申请号：US09210271

申请日：1998-12-10

Applicant: Sunit Tyagi

Inventor： Sunit Tyagi

IPC: H01L2176

CPC classification number: H01L21/76237 ,  H01L21/823892

Abstract: The present invention is a semiconductor device having and a method for forming wells by growing an epitaxial silicon layer wherein the epitaxial silicon layer has at least three silicon sublayers. The first sublayer is highly doped, the second sublayer is less doped, and the third sublayer is also highly doped. The use of the epitaxially grown wells allows for the placement of high dopant concentrations in regions of the well where electrical isolation is an issue and the placement of lower doped concentrations in regions of the well where electrical isolation is not as great an issue in order to help reduce the problem of parasitic capacitance.

Abstract translation: 本发明是具有通过生长外延硅层形成阱的方法的半导体器件，其中外延硅层具有至少三个硅子层。 第一子层是高掺杂的，第二子层较少掺杂，第三子层也是高度掺杂的。 使用外延生长的孔允许在阱的区域中放置高掺杂剂浓度，其中电隔离是问题，并且在阱的区域中放置较低的掺杂浓度，其中电绝缘不是很大的问题，以便 有助于减少寄生电容的问题。

公开(公告)号：US20120019072A1

公开(公告)日：2012-01-26

申请号：US12840130

申请日：2010-07-20

Applicant: Sunit Tyagi ,  Hemanshu Bhatt

Inventor： Sunit Tyagi ,  Hemanshu Bhatt

IPC: H02J1/10

CPC classification number: H02M7/537 ,  H02J3/383 ,  H02M7/493 ,  H02M2007/4815 ,  Y02B70/1441 ,  Y02E10/563 ,  Y10T307/50 ,  Y10T307/658 ,  Y10T307/713

Abstract: Embodiments related to the conversion of DC power to AC power are disclosed. For example, one disclosed embodiment provides a power conversion system, comprising a plurality of direct current (DC) power sources, a plurality of power output circuits connected to one another in a parallel arrangement, each power output circuit being connected to a corresponding DC power source to receive power from the corresponding DC power source and to selectively discharge power received from the corresponding DC power source, a power combiner configured to combine power received from the plurality of power output circuits to form a combined power signal, an output stage configured to convert the combined power signal into an AC signal or a DC signal, and a controller in electrical communication with each power outlet circuit and the power combiner to control the output of power by the power converter.

Abstract translation: 公开了将直流电转换为交流电力的实施例。 例如，一个公开的实施例提供了一种功率转换系统，其包括多个直流（DC）电源，多个以并联装置彼此连接的功率输出电路，每个功率输出电路连接到相应的直流电力 源极，用于从相应的直流电源接收电力并选择性地放电从相应的直流电源接收的功率;功率组合器，被配置为组合从多个功率输出电路接收的功率以形成组合的功率信号;输出级，被配置为 将组合的功率信号转换为AC信号或DC信号，以及与每个电源插座电路和功率组合器电连接的控制器，以通过功率转换器来控制功率的输出。

公开(公告)号：US07581154B2

公开(公告)日：2009-08-25

申请号：US11174003

申请日：2005-06-30

Applicant: Nivruti Rai ,  Anshumali Kumar ,  Edward Burton ,  Sunit Tyagi ,  Jeffrey L. Miller

Inventor： Nivruti Rai ,  Anshumali Kumar ,  Edward Burton ,  Sunit Tyagi ,  Jeffrey L. Miller

IPC: G11C29/00

CPC classification number: G11C11/417

Abstract: A method comprising running an error correction code on data and storing the data and the result of the error correction code in memory, running an error correction code on the data when it is read from the memory, comparing the results of the error correction codes on the data from before and after the memory, correcting errors when the comparator determines a difference in the results of the error correction codes and lowering the operating voltage of the memory array while using the error correction.

Abstract translation: 一种方法，包括在数据上运行纠错码并将数据和纠错码的结果存储在存储器中，当从存储器读取数据时对数据进行纠错码，将纠错码的结果与 来自存储器之前和之后的数据，当比较器确定误差校正码的结果的差异并且在使用纠错时降低存储器阵列的工作电压时校正错误。