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    Strained silicon MOS device with box layer between the source and drain regions
    2.
    发明申请
    Strained silicon MOS device with box layer between the source and drain regions 有权
    应变硅MOS器件，在源极和漏极区之间具有盒层

    公开(公告)号：US20070134859A1

    公开(公告)日：2007-06-14

    申请号：US11304351

    申请日：2005-12-14

    申请人： Giuseppe Curello ,  Hemant Deshpande ,  Sunit Tyagi ,  Mark Bohr

    发明人： Giuseppe Curello ,  Hemant Deshpande ,  Sunit Tyagi ,  Mark Bohr

    IPC分类号： H01L21/84

    CPC分类号： H01L29/66628 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78639 ,  H01L29/78687

    摘要： A MOS device comprises a gate stack comprising a gate electrode disposed on a gate dielectric, a first spacer and a second spacer formed on laterally opposite sides of the gate stack, a source region proximate to the first spacer, a drain region proximate to the second spacer, and a channel region subjacent to the gate stack and disposed between the source region and the drain region. The MOS device of the invention further includes a buried oxide (BOX) region subjacent to the channel region and disposed between the source region and the drain region. The BOX region enables deeper source and drain regions to be formed to reduce transistor resistance and silicide spike defects while preventing gate edge junction parasitic capacitance.

    摘要翻译： MOS器件包括栅极堆叠，其包括设置在栅极电介质上的栅极电极，形成在栅极堆叠的横向相对侧上的第一间隔物和第二间隔物，靠近第一间隔物的源极区域，靠近第二间隔区的漏极区域 间隔物和位于栅叠层下方的沟道区，并设置在源区和漏区之间。 本发明的MOS器件还包括在沟道区域的下方并设置在源极区域和漏极区域之间的掩埋氧化物（BOX）区域。 BOX区域能够形成更深的源极和漏极区域，以减少晶体管电阻和硅化物尖峰缺陷，同时防止栅极边缘结的寄生电容。

    Strained silicon MOS device with box layer between the source and drain regions
    5.
    发明授权
    Strained silicon MOS device with box layer between the source and drain regions 有权
    应变硅MOS器件，在源极和漏极区之间具有盒层

    公开(公告)号：US07422950B2

    公开(公告)日：2008-09-09

    申请号：US11304351

    申请日：2005-12-14

    申请人： Giuseppe Curello ,  Hemant V. Deshpande ,  Sunit Tyagi ,  Mark Bohr

    发明人： Giuseppe Curello ,  Hemant V. Deshpande ,  Sunit Tyagi ,  Mark Bohr

    IPC分类号： H01L21/84

    CPC分类号： H01L29/66628 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78639 ,  H01L29/78687

    摘要： A MOS device comprises a gate stack comprising a gate electrode disposed on a gate dielectric, a first spacer and a second spacer formed on laterally opposite sides of the gate stack, a source region proximate to the first spacer, a drain region proximate to the second spacer, and a channel region subjacent to the gate stack and disposed between the source region and the drain region. The MOS device of the invention further includes a buried oxide (BOX) region subjacent to the channel region and disposed between the source region and the drain region. The BOX region enables deeper source and drain regions to be formed to reduce transistor resistance and silicide spike defects while preventing gate edge junction parasitic capacitance.

    摘要翻译： MOS器件包括栅极堆叠，其包括设置在栅极电介质上的栅极电极，形成在栅极堆叠的横向相对侧上的第一间隔物和第二间隔物，靠近第一间隔物的源极区域，靠近第二间隔区的漏极区域 间隔物和位于栅叠层下方的沟道区，并设置在源区和漏区之间。 本发明的MOS器件还包括在沟道区域的下方并设置在源极区域和漏极区域之间的掩埋氧化物（BOX）区域。 BOX区域能够形成更深的源极和漏极区域，以减少晶体管电阻和硅化物尖峰缺陷，同时防止栅极边缘结的寄生电容。

    Method of fabricating a MOSFET transistor having an anti-halo for modifying narrow width device performance
    6.
    发明申请
    Method of fabricating a MOSFET transistor having an anti-halo for modifying narrow width device performance 审中-公开
    制造具有用于改变窄宽度器件性能的抗卤素的MOSFET晶体管的方法

    公开(公告)号：US20070145495A1

    公开(公告)日：2007-06-28

    申请号：US11319815

    申请日：2005-12-27

    申请人： Giuseppe Curello ,  Sivakumar Mudanai ,  Nick Lindert ,  Leonard Pipes ,  M. Shaheed ,  Sunit Tyagi

    发明人： Giuseppe Curello ,  Sivakumar Mudanai ,  Nick Lindert ,  Leonard Pipes ,  M. Shaheed ,  Sunit Tyagi

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/823481 ,  H01L21/823412

    摘要： A method including forming a transistor structure structure comprising a gate electrode over an active region of a substrate, the active region defined by a trench isolation structure and changing a performance of a narrow width transistor with respect to a wide width transistor by introducing a dopant into the active region adjacent an interface defined by the trench isolation structure and the gate electrode. A structure including a gate electrode formed on a substrate, an active region adjacent an interface defined by a trench isolation structure and a gate electrode and an implant within the active region to change a performance of a transistor.

    摘要翻译： 一种包括在衬底的有源区上形成包括栅电极的晶体管结构结构的方法，所述有源区由沟槽隔离结构限定，并且通过将掺杂剂引入到宽宽度晶体管中来改变窄宽晶体管的性能 邻接由沟槽隔离结构和栅电极限定的界面的有源区。 一种结构，包括形成在衬底上的栅电极，与由沟槽隔离结构限定的界面相邻的有源区和栅电极以及有源区内的注入以改变晶体管的性能。

    Device with stepped source/drain region profile
    7.
    发明申请
    Device with stepped source/drain region profile 有权
    具有阶梯式源极/漏极区域剖面的器件

    公开(公告)号：US20060145273A1

    公开(公告)日：2006-07-06

    申请号：US11031843

    申请日：2005-01-06

    申请人： Giuseppe Curello ,  Bernhard Sell ,  Sunit Tyagi ,  Chris Auth

    发明人： Giuseppe Curello ,  Bernhard Sell ,  Sunit Tyagi ,  Chris Auth

    IPC分类号： H01L29/94

    CPC分类号： H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7842

    摘要： Embodiments of the invention provide a transistor with stepped source and drain regions. The stepped regions may provide significant strain in a channel region while minimizing current leakage. The stepped regions may be formed by forming two recesses in a substrate to result in a stepped recess, and forming the source/drain regions in the recesses.

    摘要翻译： 本发明的实施例提供了具有阶梯式源极和漏极区域的晶体管。 台阶区域可以在通道区域中提供显着的应变，同时最小化电流泄漏。 可以通过在基板中形成两个凹槽来形成阶梯状区域，以形成阶梯状凹陷，并且在凹部中形成源极/漏极区域。