ARRAY DEVICE INCLUDING NEUROMORPHIC ELEMENT AND NEURAL NETWORK SYSTEM

    公开(公告)号:US20200210818A1

    公开(公告)日:2020-07-02

    申请号:US16325259

    申请日:2018-08-03

    Inventor: Yukio TERASAKI

    Abstract: An array device includes: a first array area that includes a neuromorphic element which is configured to multiply a signal by a weight corresponding to a variable characteristic value and outputs a first signal which is a result of processing an input signal using the neuromorphic element; and a retention unit that is able to retain the first signal output from the first array area or a second signal which is output when the first signal is input to a predetermined computing unit and is configured to input the retained first signal or the retained second signal to the first array area.

    MAGNETIC DOMAIN WALL DISPLACEMENT TYPE MAGNETIC RECORDING ELEMENT AND MAGNETIC RECORDING ARRAY

    公开(公告)号:US20200044141A1

    公开(公告)日:2020-02-06

    申请号:US16191893

    申请日:2018-11-15

    Abstract: A magnetic domain wall displacement type magnetic recording element which comprises: a first magnetization fixed part which is stacked in a first direction, a magnetic recording layer which includes a magnetic domain wall and extends in a second direction which crosses with the first direction, a non-magnetic layer which is provided between the first magnetization fixed part and the magnetic recording layer, and a first via part which is electrically connected to the magnetic recording layer, wherein at least a part of the first via part is located at a position which is apart from the first magnetization fixed part in the second direction in planar view observed from the first direction, the magnetic recording layer includes a first part which has a position where the first magnetization fixed part overlaps with the magnetic recording layer in planar view observed from the first direction, and a width of the first via part in a third direction which is orthogonal to the second direction is larger than a width of said position of the first part of the magnetic recording layer.

    NODE AND RESERVOIR DEVICE
    13.
    发明申请

    公开(公告)号:US20250036931A1

    公开(公告)日:2025-01-30

    申请号:US18784000

    申请日:2024-07-25

    Abstract: The node includes a first input terminal, a second input terminal, a first sample and hold circuit, and a first output terminal. The first input terminal is configured to be connectable to an input source for transmitting an input signal to a reservoir device. The second input terminal is configured to be connectable to at least one other node. A first terminal of the first sample and hold circuit is connected to the first input terminal and the second input terminal. A second terminal of the first sample and hold circuit is connected to the first output terminal. The first output terminal is configured to be connectable to at least one other node. The first sample and hold circuit holds and converts a joined signal of the input signal and a propagated signal from the second input terminal.

    NEUROMORPHIC DEVICE AND METHOD OF CONTROLLING NEUROMORPHIC DEVICE

    公开(公告)号:US20240346305A1

    公开(公告)日:2024-10-17

    申请号:US18631945

    申请日:2024-04-10

    Inventor: Yukio TERASAKI

    CPC classification number: G06N3/065 H10N50/10 H10N50/85 H10N59/00

    Abstract: A neuromorphic device includes a control unit. The control unit is configured to be connectable to a memristor having electrical characteristics in which conductance change occurs stochastically when a writing signal is applied to the memristor and is configured to apply the writing signal to the memristor. The writing signal is determined based on a necessary value of the conductance change amount of the memristor which is calculated from an update value of a weight of a neural network and an expected value by which the conductance of the memristor changes when a reference writing signal is applied to the memristor.

    NEUROMORPHIC DEVICE AND METHOD OF CONTROLLING NEUROMORPHIC DEVICE

    公开(公告)号:US20240346301A1

    公开(公告)日:2024-10-17

    申请号:US18133186

    申请日:2023-04-11

    Inventor: Yukio TERASAKI

    CPC classification number: G06N3/065 G06N3/049

    Abstract: A neuromorphic device includes a control unit. The control unit is configured to be connectable to a memristor having electrical characteristics in which conductance change occurs stochastically when a writing signal is applied to the memristor and is configured to apply the writing signal to the memristor. The writing signal is determined based on a necessary value of the conductance change amount of the memristor which is calculated from an update value of a weight of a neural network and an expected value by which the conductance of the memristor changes when a reference writing signal is applied to the memristor.

    SIGNAL PROCESSOR
    16.
    发明公开
    SIGNAL PROCESSOR 审中-公开

    公开(公告)号:US20240178854A1

    公开(公告)日:2024-05-30

    申请号:US18240854

    申请日:2023-08-31

    Inventor: Yukio TERASAKI

    CPC classification number: H03M1/1245 H03M1/50

    Abstract: A signal processor includes an input unit, an analog-digital converter, and a reservoir unit. The input unit receives an input of a first analog signal. The analog-digital converter converts the first analog signal to a first digital signal. The reservoir unit receives an input of at least a part of the first digital signal. The reservoir unit determines a rule of a timing at which a control signal for extracting a part of the first analog signal or the first digital signal is output.

    NEUROMORPHIC CIRCUIT, NEUROMORPHIC ARRAY LEARNING METHOD, AND PROGRAM

    公开(公告)号:US20210312272A1

    公开(公告)日:2021-10-07

    申请号:US17287355

    申请日:2018-12-20

    Inventor: Yukio TERASAKI

    Abstract: A control device of an array including neuromorphic elements that multiply a signal by a weight corresponding to a value of a variable characteristic is provided with a control unit which calculates update amounts of element conductances in a neuromorphic array on the basis of weight update amounts from a learning algorithm, and, after applying a write signal for changing conductances in the neuromorphic array, selects certain elements with reference to a predetermined threshold value and applies an additional write signal.

    NEURAL NETWORK DEVICE, SIGNAL GENERATION METHOD, AND PROGRAM

    公开(公告)号:US20200293889A1

    公开(公告)日:2020-09-17

    申请号:US16826691

    申请日:2020-03-23

    Inventor: Yukio TERASAKI

    Abstract: A neural network device includes a decimation unit configured to convert a discrete value of an input signal to a discrete value having a smaller step number than a quantization step number of the input signal on the basis of a predetermined threshold value to generate a decimation signal a modulation unit configured to modulate a discrete value of the decimation signal generated by the decimation unit to generate a modulation signal indicating the discrete value of the decimation signal, and a weighting unit including a neuromorphic element configured to output a weighted signal obtained by weighting the modulation signal through multiplication of the modulation signal generated by the modulation unit by a weight according to a value of a variable characteristic.

    SUM-OF-PRODUCTS OPERATOR, SUM-OF-PRODUCTS OPERATION METHOD, LOGICAL OPERATION DEVICE, AND NEUROMORPHIC DEVICE

    公开(公告)号:US20200150927A1

    公开(公告)日:2020-05-14

    申请号:US16675423

    申请日:2019-11-06

    Inventor: Yukio TERASAKI

    Abstract: A sum-of-products operator including: a first circuit configured to generate a plurality of signals, each of which corresponds to each of a plurality of data; a second circuit including a first operation circuit configured to multiply each of the signals generated by the first circuit by a weight using a plurality of variable resistive elements having variable resistance values, and to calculate a sum of a plurality of results of multiplications; a third circuit configured to calculate a result of summing values corresponding to the data or a result of the summing value after being adjusted; and a fourth circuit including a differential circuit configured to output a difference between a calculated result in the first operation circuit of the second circuit and a calculated result in the third circuit.

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