公开(公告)号：US09082473B2

公开(公告)日：2015-07-14

申请号：US13785583

申请日：2013-03-05

Applicant: Texas Instruments Incorporated

Inventor： Abidur Rahman ,  Tatsuyuki Nihei ,  Tatsuro Sato ,  Uchino Osamu

IPC: G11C11/22 ,  G11C5/14

CPC classification number: G11C5/148 ,  G11C11/2297

Abstract: Corruption of data in a FRAM (2) is avoided by applying a regulated voltage (VLDO) to a conductive pin (5-1). A switch (SW1) is coupled between the conductive pin and a power terminal of the FRAM so a FRAM supply voltage (VFRAM) is equal to the regulated voltage when the switch is closed. The conductive pin is coupled to a power terminal of a digital circuit (3) so a digital circuit supply voltage (VCORE) is equal to the regulated voltage. A power interruption is detected to produce an interruption signal (nBORdet) that opens the switch and also prevents starting of new read and write operations in the FRAM. A sufficient FRAM supply voltage is maintained by an internal capacitor (CINT) while ongoing read and write operations in the FRAM are completed during a predetermined interval. The conductive pin may be coupled to the switch by bonding wire inductance (LWIRE) between the switch and the conductive pin to inhibit flow of transient currents between them.

Abstract translation: 通过将调节电压（VLDO）施加到导电针（5-1）来避免FRAM（2）中的数据损坏。 开关（SW1）耦合在导电引脚和FRAM的电源端子之间，因此当开关闭合时，FRAM电源电压（VFRAM）等于调节电压。 导电引脚耦合到数字电路（3）的电源端子，因此数字电路电源电压（VCORE）等于调节电压。 检测到电源中断以产生打开该开关的中断信号（nBORdet），并且还防止在FRAM中启动新的读取和写入操作。 在FRAM中进行的读写操作在预定间隔内完成时，由内部电容器（CINT）维持足够的FRAM电源电压。 可以通过在开关和导电引脚之间接合线电感（LWIRE）来将导电引脚耦合到开关，以抑制它们之间的瞬态电流的流动。

公开(公告)号：US20250112629A1

公开(公告)日：2025-04-03

申请号：US18374202

申请日：2023-09-28

Applicant: Texas Instruments Incorporated

Inventor： Eung Jung Kim ,  Xiaochun Zhao ,  Abidur Rahman ,  Sualp Aras

IPC: H03K17/0812

Abstract: An example apparatus includes: a first transistor having a first terminal, a second terminal, and a control terminal; a second transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor coupled to the first terminal of the first transistor, the second terminal of the second transistor coupled to the second terminal of the first transistor; first driver circuitry having a terminal coupled to the control terminal of the first transistor; second driver circuitry having a terminal coupled to the control terminal of the second transistor; and gate balancing circuitry having a first terminal and a second terminal, the first terminal of the gate balancing circuitry coupled to the control terminal of the first transistor and the terminal of the first driver circuitry, the second terminal of the gate balancing circuitry coupled to the control terminal of the second transistor.

公开(公告)号：US20220214226A1

公开(公告)日：2022-07-07

申请号：US17706113

申请日：2022-03-28

Applicant: Texas Instruments Incorporated

Inventor： Eung Jung Kim ,  Abidur Rahman

IPC: G01K7/02 ,  G01K7/16

Abstract: An example device includes a first temperature sensor configured to provide a first current signal indicative of a temperature of a first circuit based on a voltage of a first temperature sensing element. The first circuit includes a power switch device and the first temperature sensing element. A second temperature sensor is configured to provide a second current signal indicative of temperature of a second circuit based on a voltage of a second temperature sensing element. The second circuit includes the second temperature sensing element. A trim circuit is configured to trim current in at least one of the first temperature sensor or the second temperature sensor to compensate for mismatch between temperature coefficients of the first and second temperature sensing elements.

公开(公告)号：US20210025925A1

公开(公告)日：2021-01-28

申请号：US17069560

申请日：2020-10-13

Applicant: Texas Instruments Incorporated

Inventor： Vijay Krishnamurthy ,  Abidur Rahman ,  Min Chu ,  Sualp Aras

IPC: G01R19/10 ,  H01L29/78 ,  G01R19/00 ,  H03K17/16 ,  H01L29/735 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234

Abstract: A microelectronic device has a common terminal transistor with two or more channels, and sense transistors in corresponding areas of the channels. The channels and the sense transistors share a common node in a semiconductor substrate. The sense transistors are configured to provide sense currents that are representative of currents through the corresponding channels. The sense transistors are located so that a ratio of the channel currents to the corresponding sense currents is less than a target value of cross-talk. The microelectronic device may be implemented without a compensation circuit which provides a compensation signal used to adjust one or more of the sense currents to reduce cross-talk. A method of forming the microelectronic device, including estimating a potential distribution in the semiconductor substrate containing the common node of the common terminal transistor, and selecting locations for the sense transistors based on the estimated potential distribution, is disclosed.

公开(公告)号：US20200033198A1

公开(公告)日：2020-01-30

申请号：US16395860

申请日：2019-04-26

Applicant: Texas Instruments Incorporated

Inventor： Eung Jung Kim ,  Abidur Rahman

IPC: G01K7/02 ,  G01K7/16

Abstract: An example device includes a first temperature sensor configured to provide a first current signal indicative of a temperature of a first circuit based on a voltage of a first temperature sensing element. The first circuit includes a power switch device and the first temperature sensing element. A second temperature sensor is configured to provide a second current signal indicative of temperature of a second circuit based on a voltage of a second temperature sensing element. The second circuit includes the second temperature sensing element. A trim circuit is configured to trim current in at least one of the first temperature sensor or the second temperature sensor to compensate for mismatch between temperature coefficients of the first and second temperature sensing elements.

公开(公告)号：US20190214973A1

公开(公告)日：2019-07-11

申请号：US16119457

申请日：2018-08-31

Applicant: Texas Instruments Incorporated

Inventor： Jae Won Choi ,  Sungho Beck ,  Abidur Rahman

IPC: H03K3/012 ,  H03K17/16 ,  H02M3/26

CPC classification number: H03K3/012 ,  H02M3/26 ,  H03K17/04123 ,  H03K17/165 ,  H03K2217/0036 ,  H03K2217/0081

Abstract: Apparatus, devices, and systems to provide a low quiescent current load switch are disclosed. A disclosed load switch circuit includes a transconductor to convert a voltage to a current input to a transistor gate, the current input to the transistor gate to control the gate to deliver power to a load from a power supply. The example circuit includes a resistor to provide power from a charge pump to the gate as controlled by the transconductor. A disclosed apparatus includes a driver to control a gate of a transistor, the gate to enable the transistor to deliver power to a load from a power supply when the gate is activated, and a gate slope control to control a rate of change over time of a voltage associated with the gate to activate the gate and to disable the driver when the gate is activated.

公开(公告)号：US09871514B1

公开(公告)日：2018-01-16

申请号：US15196323

申请日：2016-06-29

Applicant: Texas Instruments Incorporated

Inventor： Kyle Schulmeyer ,  Sualp Aras ,  Abidur Rahman

IPC: H03K17/687 ,  H03K5/08 ,  H02M3/07

CPC classification number: H03K17/687 ,  H02M1/32 ,  H02M3/07 ,  H02M3/156 ,  H02M2001/0009 ,  H03K5/08 ,  H03K17/0822

Abstract: An apparatus includes a FET device having a drain terminal, source terminal and a gate terminal; a first supply voltage coupled to the drain terminal of the FET; an output terminal coupled to the source terminal of the FET; a bias current supply coupled to the gate terminal of the FET; a second supply voltage coupled to the gate terminal of the FET; a current sensing circuit coupled to output a sense current proportional to the current flowing through the FET; a current limit comparator coupled to the sense current and comparing the sense current to a predetermined limit current; a pull down current circuit coupled to remove current from the gate terminal of the FET; a current time derivative circuit coupled to the sense current and outputting a sense rate current; and a circuit coupled to receive the sense rate current and coupled to the bias current supply.

公开(公告)号：US20180006643A1

公开(公告)日：2018-01-04

申请号：US15196323

申请日：2016-06-29

Applicant: Texas Instruments Incorporated

Inventor： Kyle Schulmeyer ,  Sualp Aras ,  Abidur Rahman

IPC: H03K17/687 ,  H03K5/08 ,  H02M3/07

CPC classification number: H03K17/687 ,  H02M1/32 ,  H02M3/07 ,  H02M3/156 ,  H02M2001/0009 ,  H03K5/08 ,  H03K17/0822

Abstract: An apparatus includes a FET device having a drain terminal, source terminal and a gate terminal; a first supply voltage coupled to the drain terminal of the FET; an output terminal coupled to the source terminal of the FET; a bias current supply coupled to the gate terminal of the FET; a second supply voltage coupled to the gate terminal of the FET; a current sensing circuit coupled to output a sense current proportional to the current flowing through the FET; a current limit comparator coupled to the sense current and comparing the sense current to a predetermined limit current; a pull down current circuit coupled to remove current from the gate terminal of the FET; a current time derivative circuit coupled to the sense current and outputting a sense rate current; and a circuit coupled to receive the sense rate current and coupled to the bias current supply.

公开(公告)号：US09748376B2

公开(公告)日：2017-08-29

申请号：US15248521

申请日：2016-08-26

Applicant: Texas Instruments Incorporated

Inventor： David J Baldwin ,  Gary Eugene Daum ,  Simon John Molloy ,  Abidur Rahman

IPC: H01L29/10 ,  H01L29/78 ,  H01L27/02 ,  H01L29/66 ,  H01L21/225 ,  H01L21/762 ,  H01L21/763 ,  H01L29/08

CPC classification number: H01L29/7815 ,  H01L21/2253 ,  H01L21/76224 ,  H01L21/763 ,  H01L27/0266 ,  H01L27/027 ,  H01L29/0634 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/66719 ,  H01L29/7811

Abstract: A semiconductor device and a method of making are disclosed. The device includes a substrate, a power field effect transistor (FET), and integrated sensors including a current sensor, a high current fault sensor, and a temperature sensor. The structure of the power FET includes a drain contact region of a first conductivity type disposed in the substrate, a drain drift region of the first conductivity type disposed over the drain contact region, doped polysilicon trenches disposed in the drain drift region, a body region of a second conductivity type, opposite from the first conductivity type, disposed between the doped polysilicon trenches, a source region disposed on a lateral side of the doped polysilicon trenches and in contact with the body region, and a source contact trench that makes contact with the source region and with the doped polysilicon trenches.

公开(公告)号：US11467192B2

公开(公告)日：2022-10-11

申请号：US17069560

申请日：2020-10-13

Applicant: Texas Instruments Incorporated

Inventor： Vijay Krishnamurthy ,  Abidur Rahman ,  Min Chu ,  Sualp Aras

IPC: G01R19/10 ,  H01L29/78 ,  G01R19/00 ,  H03K17/16 ,  H01L29/735 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234

Abstract: A microelectronic device has a common terminal transistor with two or more channels, and sense transistors in corresponding areas of the channels. The channels and the sense transistors share a common node in a semiconductor substrate. The sense transistors are configured to provide sense currents that are representative of currents through the corresponding channels. The sense transistors are located so that a ratio of the channel currents to the corresponding sense currents is less than a target value of cross-talk. The microelectronic device may be implemented without a compensation circuit which provides a compensation signal used to adjust one or more of the sense currents to reduce cross-talk. A method of forming the microelectronic device, including estimating a potential distribution in the semiconductor substrate containing the common node of the common terminal transistor, and selecting locations for the sense transistors based on the estimated potential distribution, is disclosed.