公开(公告)号：US20130040449A1

公开(公告)日：2013-02-14

申请号：US13652558

申请日：2012-10-16

Applicant: Texas Instruments Incorporated

Inventor： Allan T. Mitchell ,  Keith Jarreau

IPC: H01L21/3205

CPC classification number: H01L23/552 ,  B81B7/0064 ,  H01L23/5225 ,  H01L27/11517 ,  H01L29/78633 ,  H01L2225/06537 ,  H01L2924/0002 ,  H01L2924/3025 ,  H01L2924/00

Abstract: An integrated circuit with non-volatile memory cells shielded from ultraviolet light by a shielding structure compatible with chemical-mechanical processing. The disclosed shielding structure includes a roof structure with sides; along each side are spaced-apart contact posts, each with a width on the order of the wavelength of ultraviolet light to be shielded, and spaced apart by a distance that is also on the order of the wavelength of ultraviolet light to be shielded. The contact posts may be provided in multiple rows, and extending to a diffused region or to a polysilicon ring or both. The multiple rows may be aligned with one another or staggered relative to one another.

Abstract translation: 一种具有非易失性存储单元的集成电路，通过与化学机械处理兼容的屏蔽结构来屏蔽紫外线。 所公开的屏蔽结构包括具有侧面的屋顶结构; 沿着每一侧具有间隔开的接触柱，每个接触柱具有要被屏蔽的紫外线的波长的宽度，并隔开一定距离，该距离也在要被屏蔽的紫外线的波长的数量级上。 接触柱可以设置成多排，并且延伸到扩散区域或多晶硅环或两者。 多行可以彼此对准或相互交错排列。

公开(公告)号：US10192998B2

公开(公告)日：2019-01-29

申请号：US15848741

申请日：2017-12-20

Applicant: Texas Instruments Incorporated

Inventor： Allan T. Mitchell ,  Mark Eskew

IPC: H01L29/78 ,  A01G25/16 ,  G01N27/22 ,  G01N15/06 ,  H01L29/788 ,  G01N15/00 ,  A01G25/00 ,  G01N35/00

Abstract: An atmometer system based on an analog floating-gate structure and circuit. The floating-gate circuit includes a floating-gate electrode that serves as a gate electrode for a transistor and a plate of a storage capacitor. A conductor element exposed at the surface of the integrated circuit is electrically connected to the floating-gate electrode; reference conductor elements biased to ground are also at the surface of the integrated circuit. In operation, the transistor is biased and moisture is dispensed at the surface. The drain current of the transistor changes as the floating-gate electrode discharges via the surface conductors and a conduction path presented by the moisture. The elapsed time until the drain current stabilizes indicates the evaporation rate.

公开(公告)号：US20180130901A1

公开(公告)日：2018-05-10

申请号：US15848741

申请日：2017-12-20

Applicant: Texas Instruments Incorporated

Inventor： Allan T. Mitchell ,  Mark Eskew

IPC: H01L29/788 ,  G01N15/06 ,  A01G25/16 ,  G01N27/22 ,  A01G25/00 ,  G01N15/00 ,  G01N35/00

CPC classification number: H01L29/788 ,  A01G25/00 ,  A01G25/167 ,  G01N15/0606 ,  G01N15/0656 ,  G01N27/223 ,  G01N2015/0026 ,  G01N2035/00881

Abstract: An atmometer system based on an analog floating-gate structure and circuit. The floating-gate circuit includes a floating-gate electrode that serves as a gate electrode for a transistor and a plate of a storage capacitor. A conductor element exposed at the surface of the integrated circuit is electrically connected to the floating-gate electrode; reference conductor elements biased to ground are also at the surface of the integrated circuit. In operation, the transistor is biased and moisture is dispensed at the surface. The drain current of the transistor changes as the floating-gate electrode discharges via the surface conductors and a conduction path presented by the moisture. The elapsed time until the drain current stabilizes indicates the evaporation rate.

公开(公告)号：US20150377811A1

公开(公告)日：2015-12-31

申请号：US14749875

申请日：2015-06-25

Applicant: Texas Instruments Incorporated

Inventor： Allan T. Mitchell ,  Mark Eskew

IPC: G01N27/12 ,  G01N7/16

CPC classification number: H01L29/788 ,  A01G25/00 ,  A01G25/167 ,  G01N15/0606 ,  G01N15/0656 ,  G01N27/223 ,  G01N2015/0026 ,  G01N2035/00881

Abstract: An atmometer system based on an analog floating-gate structure and circuit. The floating-gate circuit includes a floating-gate electrode that serves as a gate electrode for a transistor and a plate of a storage capacitor. A conductor element exposed at the surface of the integrated circuit is electrically connected to the floating-gate electrode; reference conductor elements biased to ground are also at the surface of the integrated circuit. In operation, the transistor is biased and moisture is dispensed at the surface. The drain current of the transistor changes as the floating-gate electrode discharges via the surface conductors and a conduction path presented by the moisture. The elapsed time until the drain current stabilizes indicates the evaporation rate.

Abstract translation: 基于模拟浮栅结构和电路的气温计系统。 浮置栅极电路包括用作晶体管的栅电极和存储电容器的栅极的浮栅电极。 暴露在集成电路表面的导体元件电连接到浮栅电极; 偏置于接地的参考导体元件也位于集成电路的表面。 在工作中，晶体管被偏置，水分在表面被分配。 晶体管的漏极电流随着浮栅电极经由表面导体和由湿气呈现的传导路径而变化。 直到漏极电流稳定的经过时间表示蒸发速率。

公开(公告)号：US20140154850A1

公开(公告)日：2014-06-05

申请号：US14172608

申请日：2014-02-04

Applicant: Texas Instruments Incorporated

Inventor： Allan T. Mitchell ,  Imran Mahmood Khan ,  Michael A. Wu

IPC: H01L29/66

CPC classification number: H01L29/66825 ,  H01L21/2652 ,  H01L23/5223 ,  H01L27/11517 ,  H01L27/1156 ,  H01L28/40 ,  H01L28/60 ,  H01L29/105 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, doped n-type throughout its length, and includes portions serving as gate electrodes of n-channel and p-channel MOS transistors; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. The p-channel MOS transistor includes a buried channel region, formed by way of ion implantation, disposed between its source and drain regions. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.

Abstract translation: 集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。 模拟浮栅电极形成为多晶硅栅极电平，在其整个长度上掺杂n型，并且包括用作n沟道和p沟道MOS晶体管的栅电极的部分; 金属对多晶硅储存电容器的板; 以及一块多至多层隧道电容器。 p沟道MOS晶体管包括通过离子注入形成的掩埋沟道区，设置在其源区和漏区之间。 硅化物阻挡二氧化硅阻止在电极上形成硅化物包层，而集成电路中的其它多晶硅结构是硅化物包覆的。