Predicting the timing of current phases of a DC-DC converter

    公开(公告)号:US10056819B1

    公开(公告)日:2018-08-21

    申请号:US15792208

    申请日:2017-10-24

    CPC classification number: H02M1/00 H02M3/04 H02M3/156 H02M2001/0012

    Abstract: A timing regulation circuit includes a fixed and tunable timer. A current source generates a source current I1 proportional to an inductor voltage ΔV1 of a DC-DC converter during an energizing phase and a current source generates a sink current I2 proportional to inductor voltage ΔV2 during a de-energizing phase. The fixed timer controls a first switch in series with I1 or I2 and the tunable timer controls a balancing switch in series with the other current. I1 or I2 is coupled by the first switch and the other current is coupled by the balancing switch to a common capacitor that provides a regulation voltage to the tunable timer which outputs a regulated duration (Tregulated) for an energizing or de-energizing phase. When Tregulated closes the balancing switch the common capacitor provides a predicted current returning inductor current to a starting value when all phases finish for providing a volt-second balance.

    Power-save mode for fixed-frequency DC-DC converter

    公开(公告)号:US12261529B2

    公开(公告)日:2025-03-25

    申请号:US17955950

    申请日:2022-09-29

    Abstract: In a circuit for DC-DC voltage converters, an amplifier has first and second inputs coupled to a reference voltage terminal and an output voltage terminal, respectively. A comparator has first and second inputs coupled to an amplifier output and a switching terminal, respectively. A logic circuit has inputs coupled to the comparator output and a clock terminal. A driver circuit has first and second inputs coupled to first and second logic outputs, respectively. A first transistor having a first control terminal coupled to the first driver output is coupled between a supply voltage terminal and the switching terminal. A second transistor is coupled between the switching terminal and a ground terminal, and has a second control terminal coupled to the second driver output. A threshold detection circuit is configured to provide a threshold signal responsive to a current through the second transistor crossing a current threshold.

    Circuit and method to generate frequency proportional current

    公开(公告)号:US10601412B2

    公开(公告)日:2020-03-24

    申请号:US15975858

    申请日:2018-05-10

    Abstract: Disclosed examples include self-biased DLL circuits to generate a bias current signal proportional to a repetition frequency of a first signal representing continuous switching or discontinued switching operation of the DC-DC converter. The DLL circuit includes a monostable multivibrator to provide a pulse output signal in response to an edge of the first signal with a pulse duration set by a control current signal, a phase detector to provide output signals according to a phase difference between an edge of the pulse output signal and the first signal, and an output circuit to provide an output signal according to the phase detector output signals and according to an offset signal, to provide the bias current signal according to the output signal, and to provide the control current signal according to the output signal.

    DC-DC converter having predicted zero inductor current

    公开(公告)号:US10340803B2

    公开(公告)日:2019-07-02

    申请号:US15135987

    申请日:2016-04-22

    Abstract: A DC-to-DC voltage converter includes a converter input for receiving a DC voltage. A first switch is coupled between the input and a first node. A second switch is coupled between the first node and a ground. An inductor is coupled between the first node and a converter output. A capacitor is coupled between the converter output and ground. An output voltage synthesizer is coupled to the converter input and the converter output for synthesizing the voltage at the first node and for generating a control signal for at least one of the first switch and the second switch in response to the voltages at the converter input and the converter output.

    Ultra-low Iq buck converter with switchable error amplifier

    公开(公告)号:US11218076B2

    公开(公告)日:2022-01-04

    申请号:US16558079

    申请日:2019-08-31

    Abstract: A switching converter circuit includes a hysteretic comparator with a reference voltage (VREF) node and a feedback node. The switching converter circuit also includes a switchable error amplifier circuit coupled to the feedback node of the hysteretic comparator. The switchable error amplifier circuit includes an error amplifier that is coupled to the feedback node during a power-save mode and that is decoupled from the feedback node during a deep power-save mode initiated in response to a duration of the power-save mode being greater than a time threshold.

Patent Agency Ranking