公开(公告)号：US20230134698A1

公开(公告)日：2023-05-04

申请号：US17514550

申请日：2021-10-29

Applicant: Texas Instruments Incorporated

Inventor： Jungwoo Joh ,  Sameer Prakash Pendharkar ,  Qhalid RS Fareed ,  Chang Soo Suh

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/66 ,  H01L29/20

Abstract: A gallium nitride (“GaN”)-based semiconductor device, and method of forming the same. In one example, the semiconductor device includes a channel layer including GaN, and a barrier layer of a first III-N material over the channel layer. The semiconductor device also includes a cap layer of a second III-N material including indium over the barrier layer, wherein the cap layer may have the effect of modifying a threshold voltage and gate leakage current of the semiconductor device.

公开(公告)号：US20220216309A1

公开(公告)日：2022-07-07

申请号：US17700147

申请日：2022-03-21

Applicant: Texas Instruments Incorporated

Inventor： Ramana Tadepalli ,  Chang Soo Suh

IPC: H01L29/40 ,  H01L29/78 ,  H01L21/768 ,  H01L23/528 ,  H01L21/66 ,  H01L23/00 ,  H01L23/31 ,  G01R31/26 ,  H01L29/778

Abstract: In a described example, an apparatus includes a transistor formed on a semiconductor substrate, the transistor including: a transistor gate and an extended drain between the transistor gate and a transistor drain contact; a transistor source contact coupled to a source contact probe pad; a first dielectric layer covering the semiconductor substrate and the transistor gate; a source field plate on the first dielectric layer and coupled to a source field plate probe pad spaced from and electrically isolated from the source contact probe pad; and the source field plate capacitively coupled through the first dielectric layer to a first portion of the extended drain.

公开(公告)号：US20250107131A1

公开(公告)日：2025-03-27

申请号：US18472329

申请日：2023-09-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sandeep R. Bahl ,  Ujwal Radhakrishna ,  Chang Soo Suh

IPC: H01L29/778 ,  H01L29/08 ,  H01L29/20 ,  H01L29/66

Abstract: The present disclosure generally relates to a conductive layer in a gate structure of a semiconductor device. The conductive layer may be a silicon layer. An example is a semiconductor device. The semiconductor device includes a channel layer, a barrier layer, a gate layer, and a silicon layer. The channel layer is over a semiconductor substrate. The barrier layer is over the channel layer. The gate layer is over the barrier layer. The silicon layer is over and contacts the gate layer.

公开(公告)号：US20230101543A1

公开(公告)日：2023-03-30

申请号：US17491259

申请日：2021-09-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Chang Soo Suh

IPC: H01L29/40

Abstract: One example described herein includes an integrated circuit (IC) that includes a gallium-nitride (GaN) transistor device. The IC includes GaN active layers that define an active region, and a gate structure arranged on a surface of the active region. The IC also includes a source arranged on a first side of the gate structure and a drain arranged on a second side of the gate structure. The IC further includes at least one source field-plate structure conductively coupled to the source and a gate-level field-plate structure that is coupled to the source.

公开(公告)号：US20240055488A1

公开(公告)日：2024-02-15

申请号：US17885879

申请日：2022-08-11

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Chang Soo Suh

IPC: H01L29/20 ,  H01L21/285 ,  H01L29/51

CPC classification number: H01L29/2003 ,  H01L21/28581 ,  H01L29/518

Abstract: A microelectronic device includes a GaN FET on a substrate such as silicon and a buffer layer of p-type GaN semiconductor material. The GaN FET includes a gate electrode extension of p-type GaN semiconductor material in electrical contact with the gate electrode. The gate electrode extension of p-type GaN semiconductor material in electrical contact with the gate electrode may improve the GaN FET characteristics such as off state leakage, subthreshold voltage and post stress Vt shift.

公开(公告)号：US20230197784A1

公开(公告)日：2023-06-22

申请号：US17559635

申请日：2021-12-22

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Qhalid Fareed ,  Sridhar Seetharaman ,  Jungwoo Joh ,  Chang Soo Suh

IPC: H01L29/08 ,  H01L29/20 ,  H01L29/06

CPC classification number: H01L29/0847 ,  H01L29/2003 ,  H01L29/0653

Abstract: An electronic device includes an one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride back barrier layer over a buffer structure, a gallium nitride layer over the back barrier layer, a hetero-epitaxy structure over the gallium nitride layer, first and second transistors over the hetero-epitaxy structure, and a hole injector having a doped gallium nitride structure over the hetero-epitaxy structure and a conductive structure partially over the doped gallium nitride structure to inject holes to form a hole layer proximate an interface of the back barrier layer and the buffer structure to mitigate vertical electric field back gating effects for the first transistor.

公开(公告)号：US20220130988A1

公开(公告)日：2022-04-28

申请号：US17081301

申请日：2020-10-27

Applicant: Texas Instruments Incorporated

Inventor： Qhalid RS Fareed ,  Dong Seup Lee ,  Jungwoo Joh ,  Chang Soo Suh

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66

Abstract: Fabrication methods, electronic devices and enhancement mode gallium nitride transistors include a gallium nitride interlayer between a hetero-epitaxy structure and a p-doped gallium nitride layer and/or between the p-doped gallium nitride layer and a gate structure to mitigate p-type dopant diffusion, improve current collapse performance, and mitigate positive-bias temperature instability. In certain examples, the interlayer or interlayers is/are fabricated using epitaxial deposition with no p-type dopant source. In certain fabrication process examples, epitaxial deposition or growth is interrupted after the depositing an aluminum gallium nitride layer of the hetero-epitaxy structure, after which growth is resumed to deposit the first gallium nitride interlayer over the aluminum gallium nitride layer to mitigate p-type dopant diffusion and current collapse.

公开(公告)号：US11302785B2

公开(公告)日：2022-04-12

申请号：US16444936

申请日：2019-06-18

Applicant: Texas Instruments Incorporated

Inventor： Ramana Tadepalli ,  Chang Soo Suh

IPC: H01L21/66 ,  G01R31/26 ,  H01L21/44 ,  H01L21/48 ,  H01L29/40 ,  H01L29/78 ,  H01L21/768 ,  H01L23/528 ,  H01L23/00 ,  H01L23/31 ,  H01L29/778 ,  H01L29/20 ,  H01L29/24

Abstract: In a described example, an apparatus includes a transistor formed on a semiconductor substrate, the transistor including: a transistor gate and an extended drain between the transistor gate and a transistor drain contact; a transistor source contact coupled to a source contact probe pad; a first dielectric layer covering the semiconductor substrate and the transistor gate; a source field plate on the first dielectric layer and coupled to a source field plate probe pad spaced from and electrically isolated from the source contact probe pad; and the source field plate capacitively coupled through the first dielectric layer to a first portion of the extended drain.

公开(公告)号：US10680093B2

公开(公告)日：2020-06-09

申请号：US15864157

申请日：2018-01-08

Applicant: Texas Instruments Incorporated

Inventor： Jungwoo Joh ,  Naveen Tipirneni ,  Chang Soo Suh ,  Sameer Pendharkar

IPC: H01L29/778 ,  H01L21/265 ,  H01L21/266 ,  H01L21/308 ,  H01L29/06 ,  H01L29/08 ,  H01L29/20 ,  H01L29/417 ,  H01L29/66

Abstract: A High Electron Mobility Transistor (HEMT) includes an active layer on a substrate, and a Group IIIA-N barrier layer on the active layer. An isolation region is through the barrier layer to provide at least one isolated active area including the barrier layer on the active layer. A gate is over the barrier layer. A drain includes at least one drain finger including a fingertip having a drain contact extending into the barrier layer to contact to the active layer and a source having a source contact extending into the barrier layer to contact to the active layer. The source forms a loop that encircles the drain. The isolation region includes a portion positioned between the source and drain contact so that there is a conduction barrier in a length direction between the drain contact of the fingertip and the source.

公开(公告)号：US10381456B2

公开(公告)日：2019-08-13

申请号：US15587021

申请日：2017-05-04

Applicant: Texas Instruments Incorporated

Inventor： Chang Soo Suh ,  Dong Seup Lee ,  Jungwoo Joh ,  Naveen Tipirneni ,  Sameer Prakash Pendharkar

IPC: H01L29/778 ,  H01L29/66 ,  H01L23/535 ,  H01L29/10 ,  H01L21/8252 ,  H01L27/06 ,  H01L27/085 ,  H01L29/20 ,  H01L27/07 ,  H01L27/088

Abstract: An enhancement-mode High Electron Mobility Transistor (HEMT) includes a substrate, a Group IIIA-N active layer on the substrate, a Group IIIA-N barrier layer on the active layer, and at least one isolation region through the barrier layer to provide an isolated active area having the barrier layer on the active layer. A p-GaN layer is on the barrier layer. A tunnel diode in the gate stack includes an n-GaN layer on an InGaN layer on the p-GaN layer. A gate electrode is over the n-GaN layer. A drain having a drain contact is on the barrier layer to provide contact to the active layer, and a source having a source contact is on the barrier layer provides contact to the active layer. The tunnel diode provides a gate contact to eliminate the need to form a gate contact directly to the p-GaN layer.