公开(公告)号：US12046666B2

公开(公告)日：2024-07-23

申请号：US17330012

申请日：2021-05-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chang Soo Suh ,  Sameer Prakash Pendharkar ,  Naveen Tipirneni ,  Jungwoo Joh

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/308 ,  H01L29/20 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/778 ,  H01L21/0254 ,  H01L21/308 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/42312 ,  H01L29/66462

Abstract: In some examples, a gallium nitride (GaN)-based transistor, comprises a substrate; a GaN layer supported by the substrate; an aluminum nitride gallium (AlGaN) layer supported by the GaN layer; a p-doped GaN structure supported by the AlGaN layer; and multiple p-doped GaN blocks supported by the AlGaN layer, each of the multiple p-doped GaN blocks physically separated from the remaining multiple p-doped GaN blocks, wherein first and second contours of a two-dimensional electron gas (2DEG) of the GaN-based transistor are at an interface of the AlGaN and GaN layers.

公开(公告)号：US11888027B2

公开(公告)日：2024-01-30

申请号：US17559635

申请日：2021-12-22

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Qhalid Fareed ,  Sridhar Seetharaman ,  Jungwoo Joh ,  Chang Soo Suh

IPC: H01L29/00 ,  H01L29/08 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L29/0847 ,  H01L29/0653 ,  H01L29/2003

Abstract: An electronic device includes an one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride back barrier layer over a buffer structure, a gallium nitride layer over the back barrier layer, a hetero-epitaxy structure over the gallium nitride layer, first and second transistors over the hetero-epitaxy structure, and a hole injector having a doped gallium nitride structure over the hetero-epitaxy structure and a conductive structure partially over the doped gallium nitride structure to inject holes to form a hole layer proximate an interface of the back barrier layer and the buffer structure to mitigate vertical electric field back gating effects for the first transistor.

公开(公告)号：US11177378B2

公开(公告)日：2021-11-16

申请号：US16895111

申请日：2020-06-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jungwoo Joh ,  Naveen Tipirneni ,  Chang Soo Suh ,  Sameer Pendharkar

IPC: H01L29/778 ,  H01L21/265 ,  H01L21/266 ,  H01L21/308 ,  H01L29/06 ,  H01L29/08 ,  H01L29/20 ,  H01L29/417 ,  H01L29/66

Abstract: A High Electron Mobility Transistor (HEMT) includes an active layer on a substrate, and a Group IIIA-N barrier layer on the active layer. An isolation region is through the barrier layer to provide at least one isolated active area including the barrier layer on the active layer. A gate is over the barrier layer. A drain includes at least one drain finger including a fingertip having a drain contact extending into the barrier layer to contact to the active layer and a source having a source contact extending into the barrier layer to contact to the active layer. The source forms a loop that encircles the drain. The isolation region includes a portion positioned between the source and drain contact so that there is a conduction barrier in a length direction between the drain contact of the fingertip and the source.

公开(公告)号：US20240274705A1

公开(公告)日：2024-08-15

申请号：US18625366

申请日：2024-04-03

Applicant: Texas Instruments Incorporated

Inventor： Chang Soo Suh ,  Jungwoo Joh ,  Dong Seup Lee ,  Shoji Wada ,  Karen Hildegard Ralston Kirmse

IPC: H01L29/778 ,  B82Y30/00 ,  B82Y40/00 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/66462 ,  B82Y30/00 ,  B82Y40/00

Abstract: A semiconductor device includes a gallium nitride based low threshold depletion mode transistor (GaN FET) with a threshold potential between −10 volts and −0.5 volts. The GaN FET has a channel layer of III-N semiconductor material including gallium and nitrogen that supports a two-dimensional electron gas (2DEG). The GaN FET has a barrier layer of III-N semiconductor material including aluminum and nitrogen over the channel layer. The GaN FET further has a p-type gate of III-N semiconductor material including gallium and nitrogen. A bottom surface of the gate, adjacent to the barrier layer, does not extend past a top surface of the barrier layer, located opposite from the channel layer. The GaN FET is free of a dielectric layer between the gate and the barrier layer.

公开(公告)号：US11978790B2

公开(公告)日：2024-05-07

申请号：US17108892

申请日：2020-12-01

Applicant: Texas Instruments Incorporated

Inventor： Chang Soo Suh ,  Jungwoo Joh ,  Dong Seup Lee ,  Shoji Wada ,  Karen Hildegard Ralston Kirmse

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  B82Y30/00 ,  B82Y40/00

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/66462 ,  B82Y30/00 ,  B82Y40/00

Abstract: A semiconductor device includes a gallium nitride based low threshold depletion mode transistor (GaN FET) with a threshold potential between −10 volts and −0.5 volts. The GaN FET has a channel layer of III-N semiconductor material including gallium and nitrogen that supports a two-dimensional electron gas (2DEG). The GaN FET has a barrier layer of III-N semiconductor material including aluminum and nitrogen over the channel layer. The GaN FET further has a p-type gate of III-N semiconductor material including gallium and nitrogen. A bottom surface of the gate, adjacent to the barrier layer, does not extend past a top surface of the barrier layer, located opposite from the channel layer. The GaN FET is free of a dielectric layer between the gate and the barrier layer.

公开(公告)号：US20240120383A1

公开(公告)日：2024-04-11

申请号：US18543738

申请日：2023-12-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee ,  Qhalid Fareed ,  Sridhar Seetharaman ,  Jungwoo Joh ,  Chang Soo Suh

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L29/0847 ,  H01L29/0653 ,  H01L29/2003

Abstract: An electronic device includes an one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride back barrier layer over a buffer structure, a gallium nitride layer over the back barrier layer, a hetero-epitaxy structure over the gallium nitride layer, first and second transistors over the hetero-epitaxy structure, and a hole injector having a doped gallium nitride structure over the hetero-epitaxy structure and a conductive structure partially over the doped gallium nitride structure to inject holes to form a hole layer proximate an interface of the back barrier layer and the buffer structure to mitigate vertical electric field back gating effects for the first transistor.

公开(公告)号：US20220173234A1

公开(公告)日：2022-06-02

申请号：US17108892

申请日：2020-12-01

Applicant: Texas Instruments Incorporated

Inventor： Chang Soo Suh ,  Jungwoo Joh ,  Dong Seup Lee ,  Shoji Wada ,  Karen Hildegard Ralston Kirmse

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20

Abstract: A semiconductor device includes a gallium nitride based low threshold depletion mode transistor (GaN FET) with a threshold potential between −10 volts and −0.5 volts. The GaN FET has a channel layer of III-N semiconductor material including gallium and nitrogen that supports a two-dimensional electron gas (2 DEG). The GaN FET has a barrier layer of III-N semiconductor material including aluminum and nitrogen over the channel layer. The GaN FET further has a p-type gate of III-N semiconductor material including gallium and nitrogen. A bottom surface of the gate, adjacent to the barrier layer, does not extend past a top surface of the barrier layer, located opposite from the channel layer. The GaN FET is free of a dielectric layer between the gate and the barrier layer.

公开(公告)号：US11049960B2

公开(公告)日：2021-06-29

申请号：US16294687

申请日：2019-03-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chang Soo Suh ,  Sameer Prakash Pendharkar ,  Naveen Tipirneni ,  Jungwoo Joh

IPC: H01L29/872 ,  H01L29/205 ,  H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/423 ,  H01L21/308 ,  H01L29/417 ,  H01L21/02

Abstract: In some examples, a gallium nitride (GaN)-based transistor, comprises a substrate; a GaN layer supported by the substrate; an aluminum nitride gallium (AlGaN) layer supported by the GaN layer; a p-doped GaN structure supported by the AlGaN layer; and multiple p-doped GaN blocks supported by the AlGaN layer, each of the multiple p-doped GaN blocks physically separated from the remaining multiple p-doped GaN blocks, wherein first and second contours of a two-dimensional electron gas (2DEG) of the GaN-based transistor are at an interface of the AlGaN and GaN layers.

公开(公告)号：US10707324B2

公开(公告)日：2020-07-07

申请号：US16456040

申请日：2019-06-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chang Soo Suh ,  Dong Seup Lee ,  Jungwoo Joh ,  Naveen Tipirneni ,  Sameer Prakash Pendharkar

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/10 ,  H01L21/8252 ,  H01L27/06 ,  H01L27/085 ,  H01L23/535 ,  H01L29/20 ,  H01L27/07 ,  H01L27/088

Abstract: One example provides an enhancement-mode High Electron Mobility Transistor (HEMT) includes a substrate, a Group IIIA-N active layer over the substrate, a Group IIIA-N barrier layer over the active layer, and at least one isolation region through the barrier layer to provide an isolated active area having the barrier layer on the active layer. A gate stack is located between source and drain contacts to the active layer. A tunnel diode in the gate stack includes an n-GaN layer on an InGaN layer on a p-GaN layer located on the barrier layer.

公开(公告)号：US20250120157A1

公开(公告)日：2025-04-10

申请号：US18610150

申请日：2024-03-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jonas Höhenberger ,  Ujwal Radhakrishna ,  Michael Lueders ,  Meng-Chia Lee ,  Chang Soo Suh ,  Zhikai Tang ,  Jungwoo Joh ,  Timothy Bryan Merkin ,  Stefan Herzer ,  Bernhard Ziegltrum ,  Helmut Rinck ,  Michael Hans Enzelberger-Heim ,  Ercuement Hasanoglu

IPC: H01L29/40 ,  H01L21/027 ,  H01L21/311 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

Abstract: The present disclosure generally relates to a semiconductor device having a slanted field plate. In an example, a semiconductor device includes a semiconductor substrate, a gate, a drain contact, a source contact, and a field plate. The gate is on a surface of the semiconductor substrate. The drain contact and a source contact are on the semiconductor substrate. The field plate is over the surface of the semiconductor substrate and extends from one side of the gate towards the drain contact. The field plate includes multiple field plate portions. Each of the multiple field plate portions has a uniform respective slope with respect to the surface, and the multiple field plate portions have different slopes.