公开(公告)号：US20160307831A1

公开(公告)日：2016-10-20

申请号：US15194254

申请日：2016-06-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dan Okamoto

IPC: H01L23/498 ,  H01L21/683 ,  H01L23/31 ,  H01L21/48 ,  H01L23/495 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49805 ,  H01L21/4821 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/4839 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3185 ,  H01L23/495 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/96 ,  H01L2221/68372 ,  H01L2221/68386 ,  H01L2224/48175 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/1816 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A method of making a flat no lead package including attaching a first plurality of leads in spaced apart relationship in a predetermined pattern on a tape and attaching a first die to the tape at a predetermined position within the predetermined lead pattern.

Abstract translation: 一种制造扁平的无引线封装的方法，包括以预定图案以带间隔的关系附接第一多个引线并将第一裸片附接到预定引线图案中的预定位置处的带上。

公开(公告)号：US09379087B2

公开(公告)日：2016-06-28

申请号：US14535939

申请日：2014-11-07

Applicant: Texas Instruments Incorporated

Inventor： Dan Okamoto

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  G03F7/20

CPC classification number: H01L23/49805 ,  H01L21/4821 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/4839 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3185 ,  H01L23/495 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/96 ,  H01L2221/68372 ,  H01L2221/68386 ,  H01L2224/48175 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/1816 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A method of making a flat no lead package including attaching a first plurality of leads in spaced apart relationship in a predetermined pattern on a tape and attaching a first die to the tape at a predetermined position within the predetermined lead pattern.

Abstract translation: 一种制造扁平的无引线封装的方法，包括以预定图案以带间隔的关系附接第一多个引线并将第一裸片附接到预定引线图案中的预定位置处的带上。

公开(公告)号：US20150340324A1

公开(公告)日：2015-11-26

申请号：US14284644

申请日：2014-05-22

Applicant: Texas Instruments Incorporated

Inventor： Kazunori Hayata ,  Yohei Koto ,  Dan Okamoto

IPC: H01L23/544 ,  H01L23/31 ,  H01L21/78

CPC classification number: H01L23/544 ,  H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/03466 ,  H01L2224/04026 ,  H01L2224/056 ,  H01L2224/27013 ,  H01L2224/29101 ,  H01L2224/29298 ,  H01L2224/83815 ,  H01L2224/83855 ,  H01L2924/10158 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor package assembly includes a substrate having an upper surface with a die attachment region thereon. A layer of die attachment material is positioned on top of the die attachment region. The semiconductor package assembly also includes an integrated circuit (“IC”) die. The die has a top portion including a laterally extending top wall surface and a plurality of generally vertically extending wall surfaces extending downwardly from the top wall surface. The die has a metallized bottom portion. The bottom portion has at least two metallized laterally extending wall surfaces and a plurality of metallized generally vertically extending connecting surfaces that connect the metallized laterally extending surfaces of the bottom portion. The layer of die attachment material interfaces with one or both of the metallized laterally extending surfaces and the plurality of metallized generally vertically extending connecting wall surfaces.

Abstract translation: 半导体封装组件包括具有上表面的衬底，其上具有管芯附接区域。 一层模具附着材料位于模具附接区域的顶部。 半导体封装组件还包括集成电路（“IC”）管芯。 模具具有顶部，其包括横向延伸的顶壁表面和从顶壁表面向下延伸的多个大致垂直延伸的壁表面。 模具具有金属化的底部部分。 底部具有至少两个金属化横向延伸的壁表面和连接底部的金属化侧向延伸表面的多个金属化的大致垂直延伸的连接表面。 管芯附着材料层与金属化侧向延伸表面中的一个或两个和多个金属化的大体垂直延伸的连接壁表面相接合。