公开(公告)号：US20150381190A1

公开(公告)日：2015-12-31

申请号：US14753940

申请日：2015-06-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jagdish Chand GOYAL ,  Krishnaswamy THIAGARAJAN ,  Jayawardan JANARDHANAN ,  Srikanth MANIAN

IPC: H03L7/093 ,  H03L7/089 ,  H03L7/081 ,  H04B1/40

CPC classification number: H04B1/40 ,  H03L7/1075 ,  H03L7/1976

Abstract: A frequency synthesizer that includes a reference frequency scaler and a phase locked loop (PLL) coupled to the reference frequency scaler. The reference frequency scaler is configured to generate a first reference frequency and a second reference frequency. The PLL is configured to generate a first output frequency based on the first reference frequency during a first timeslot and a second output frequency based on the second reference frequency during a second timeslot. The PLL comprises a loop filter that includes a first switch connected in series to a first capacitor and configured to close during the first timeslot and a second switch connected in series to a second capacitor and configured to open during the first timeslot.

Abstract translation: 一种频率合成器，其包括参考频率缩放器和耦合到参考频率缩放器的锁相环（PLL）。 参考频率缩放器被配置为产生第一参考频率和第二参考频率。 PLL被配置为在第一时隙期间基于第一参考频率产生第一输出频率，并且在第二时隙期间基于第二参考频率产生第二输出频率。 PLL包括环路滤波器，其包括串联连接到第一电容器并被配置为在第一时隙期间闭合的第一开关和与第二电容器串联连接并被配置为在第一时隙期间断开的第二开关。

公开(公告)号：US20240035851A1

公开(公告)日：2024-02-01

申请号：US18480003

申请日：2023-10-03

Applicant: Texas Instruments Incorporated

Inventor： Jayawardan JANARDHANAN ,  Sandeep RAO ,  Goutam DUTTA

IPC: G01C22/00 ,  G01C21/18 ,  G06F1/16 ,  G01C21/20 ,  G01P15/00 ,  G01C21/16

CPC classification number: G01C22/006 ,  G01C21/18 ,  G06F1/163 ,  G01C21/206 ,  G01P15/00 ,  G01C21/165 ,  G01C21/185 ,  G01C21/188 ,  G01F15/00

Abstract: A system for pedestrian use includes an accelerometer having multiple electronic sensors; an electronic circuit operable to generate a signal stream representing magnitude of overall acceleration sensed by the accelerometer, and to electronically correlate a sliding window of the signal stream with itself to produce peaks at least some of which represent walking steps, and further operable to electronically execute a periodicity check to compare different step periods for similarity, and if sufficiently similar then to update a portion of the circuit substantially representing a walking-step count; and an electronic display responsive to the electronic circuit to display information at least in part based on the step count. Other systems, electronic circuits and processes are disclosed.

公开(公告)号：US20200021301A1

公开(公告)日：2020-01-16

申请号：US16582341

申请日：2019-09-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jayawardan JANARDHANAN ,  Christopher Andrew SCHELL ,  Arvind SRIDHAR ,  Sinjeet Dhanvantray PAREKH

IPC: H03L7/093 ,  H03L7/083 ,  H03L7/087 ,  H03L7/14

Abstract: A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.

公开(公告)号：US20190288694A1

公开(公告)日：2019-09-19

申请号：US16226938

申请日：2018-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sinjeet Dhanvantray PAREKH ,  Eric Paul LINDGREN ,  Christopher Andrew SCHELL ,  Jayawardan JANARDHANAN

IPC: H03L7/07 ,  H03K5/13 ,  H03L7/093

Abstract: A phase-locked loop (PLL) includes a selection circuit including a plurality of inputs, each input to receive a separate reference clock. A programmable reference clock divider divides down the reference clock selected by the selection circuit to generate a divided down reference clock. A feedback clock divider divides down an output clock from the PLL to generate a feedback clock. A time-to-digital converter (TDC) generates a digital output value based on a phase difference between the divided down reference clock and the feedback clock. A circuit including a finite state machine, causes, responsive to an indication to change reference clocks, the reference clock divider and the feedback clock divider to be held in a reset state, the divide ratio of the reference clock divider to be modified, and then to release the reset state.

公开(公告)号：US20190280699A1

公开(公告)日：2019-09-12

申请号：US16233283

申请日：2018-12-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jayawardan JANARDHANAN ,  Christopher Andrew SCHELL ,  Arvind SRIDHAR ,  Sinjeet Dhanvantray PAREKH

IPC: H03L7/093 ,  H03L7/083 ,  H03L7/087 ,  H03L7/14

Abstract: A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.

公开(公告)号：US20170250693A1

公开(公告)日：2017-08-31

申请号：US15443217

申请日：2017-02-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jayawardan JANARDHANAN ,  Krishnaswamy THIAGARAJAN ,  Jagdish Chand GOYAL

IPC: H03L7/087

CPC classification number: H03L7/087 ,  H03L7/0895 ,  H03L7/1072 ,  H03L7/113

Abstract: A phase lock loop (PLL) includes a voltage-controlled oscillator (VCO) and a frequency detector to generate a FAST signal responsive to a frequency of a reference signal being greater than the frequency of a feedback signal derived from the VCO and to generate a SLOW signal responsive to the frequency of the reference signal being smaller than the frequency of the feedback signal. The PLL also includes a digital charge pump, a loop filter, and a state machine circuit. Responsive to receipt of multiple consecutive FAST signals when the digital charge pump is providing a charging current to the loop filter, the state machine circuit reconfigures the digital charge pump to increase the charging current to the loop filter. Responsive to receipt of multiple consecutive SLOW signals when the loop filter is discharging, the state machine circuit reconfigures the digital charge pump to cause the loop filter's discharge current to increase. Upon detection of a terminal condition, the state machine circuit may disable the digital charge pump and enable operation of an analog charge pump.