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    CRYSTAL OSCILLATOR OFFSET TRIM IN A PHASE-LOCKED LOOP
    6.
    发明申请
    CRYSTAL OSCILLATOR OFFSET TRIM IN A PHASE-LOCKED LOOP 审中-公开

    公开(公告)号：US20190288699A1

    公开(公告)日：2019-09-19

    申请号：US16227777

    申请日：2018-12-20

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sinjeet Dhanvantray PAREKH ,  Jayawardan JANARDHANAN ,  Christopher Andrew SCHELL ,  Arvind SRIDHAR

    IPC: H03L7/099 ,  H03L7/093

    Abstract: A phase-locked loop (PLL) includes a time-to-digital converter (TDC) to receive a reference clock. The PLL also includes a digital loop filter coupled to the TDC. The digital loop filter repeatedly generates frequency control words. An analog phase-locked loop (APLL) includes a programmable frequency divider. A non-volatile memory device stores a value from the digital loop filter. The PLL includes a free-run control circuit. Upon a power-on reset process, the free-run circuit retrieves the value from the non-volatile memory to adjust a divide ratio of the programmable frequency divider based on the retrieved value. Upon a reference clock provided to the TDC, the free-run control circuit continues to adjust the divide ratio of the programmable frequency divider based on both the retrieved value from the non-volatile memory and a current frequency control word from the digital loop filter.

    CORRUPTED CLOCK DETECTION CIRCUIT FOR A PHASE-LOCKED LOOP
    7.
    发明申请
    CORRUPTED CLOCK DETECTION CIRCUIT FOR A PHASE-LOCKED LOOP 审中-公开

    公开(公告)号：US20190280695A1

    公开(公告)日：2019-09-12

    申请号：US16232893

    申请日：2018-12-26

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Eric Paul LINDGREN ,  Arvind SRIDHAR ,  Jayawardan JANARDHANAN

    IPC: H03L7/085

    Abstract: A selection circuit receives a plurality of reference clocks. The selection circuit is controlled by a control signal to output one of the plurality of reference clocks. A phase-locked loop couples to an output of the selection circuit and uses the selected reference clock for phase locking an output clock. A plurality of reference clock window detector circuits is included. Each reference clock window detector circuit receives a separate reference clock. Each reference clock window detector circuit asserts an error signal responsive to an early reference clock edge error in which the reference clock window detector circuit detects a reference clock edge before expiration of an early time window. Further, each reference clock window detector circuit asserts the error signal responsive to a late reference clock edge error in which the reference clock window detector circuit detects a reference clock edge after expiration of a late time window.

    THREE LOOP PHASE-LOCKED LOOP
    9.
    发明申请
    THREE LOOP PHASE-LOCKED LOOP 审中-公开

    公开(公告)号：US20190288695A1

    公开(公告)日：2019-09-19

    申请号：US16233972

    申请日：2018-12-27

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Henry YAO ,  Arvind SRIDHAR ,  Sinjeet Dhanvantray PAREKH ,  Jayawardan JANARDHANAN

    IPC: H03L7/087 ,  H03L7/099 ,  H03L7/197

    Abstract: A phase-locked loop (PLL) system includes a first PLL coupled to receive a first reference clock. The PLL system also includes a second PLL coupled to receive a second reference clock. The output of the second PLL is coupled to the first PLL, and the second PLL is configured to control the first PLL. The PLL system further includes a third PLL coupled to receive an input reference clock. The output of the third PLL is coupled to the second PLL. The third PLL is configured to control the second PLL.

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