公开(公告)号：US20150381190A1

公开(公告)日：2015-12-31

申请号：US14753940

申请日：2015-06-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jagdish Chand GOYAL ,  Krishnaswamy THIAGARAJAN ,  Jayawardan JANARDHANAN ,  Srikanth MANIAN

IPC: H03L7/093 ,  H03L7/089 ,  H03L7/081 ,  H04B1/40

CPC classification number: H04B1/40 ,  H03L7/1075 ,  H03L7/1976

Abstract: A frequency synthesizer that includes a reference frequency scaler and a phase locked loop (PLL) coupled to the reference frequency scaler. The reference frequency scaler is configured to generate a first reference frequency and a second reference frequency. The PLL is configured to generate a first output frequency based on the first reference frequency during a first timeslot and a second output frequency based on the second reference frequency during a second timeslot. The PLL comprises a loop filter that includes a first switch connected in series to a first capacitor and configured to close during the first timeslot and a second switch connected in series to a second capacitor and configured to open during the first timeslot.

Abstract translation: 一种频率合成器，其包括参考频率缩放器和耦合到参考频率缩放器的锁相环（PLL）。 参考频率缩放器被配置为产生第一参考频率和第二参考频率。 PLL被配置为在第一时隙期间基于第一参考频率产生第一输出频率，并且在第二时隙期间基于第二参考频率产生第二输出频率。 PLL包括环路滤波器，其包括串联连接到第一电容器并被配置为在第一时隙期间闭合的第一开关和与第二电容器串联连接并被配置为在第一时隙期间断开的第二开关。

公开(公告)号：US20170250693A1

公开(公告)日：2017-08-31

申请号：US15443217

申请日：2017-02-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jayawardan JANARDHANAN ,  Krishnaswamy THIAGARAJAN ,  Jagdish Chand GOYAL

IPC: H03L7/087

CPC classification number: H03L7/087 ,  H03L7/0895 ,  H03L7/1072 ,  H03L7/113

Abstract: A phase lock loop (PLL) includes a voltage-controlled oscillator (VCO) and a frequency detector to generate a FAST signal responsive to a frequency of a reference signal being greater than the frequency of a feedback signal derived from the VCO and to generate a SLOW signal responsive to the frequency of the reference signal being smaller than the frequency of the feedback signal. The PLL also includes a digital charge pump, a loop filter, and a state machine circuit. Responsive to receipt of multiple consecutive FAST signals when the digital charge pump is providing a charging current to the loop filter, the state machine circuit reconfigures the digital charge pump to increase the charging current to the loop filter. Responsive to receipt of multiple consecutive SLOW signals when the loop filter is discharging, the state machine circuit reconfigures the digital charge pump to cause the loop filter's discharge current to increase. Upon detection of a terminal condition, the state machine circuit may disable the digital charge pump and enable operation of an analog charge pump.

公开(公告)号：US20150326236A1

公开(公告)日：2015-11-12

申请号：US14709759

申请日：2015-05-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Krishnaswamy THIAGARAJAN ,  Jagdish Chand GOYAL ,  Srikanth MANIAN ,  Debapriya SAHU

IPC: H03L7/197 ,  H04L7/033 ,  H04B1/40

CPC classification number: H03L7/1976 ,  H03L7/0814 ,  H03L7/1974 ,  H03L2207/10 ,  H04B1/40 ,  H04L7/033 ,  H04L7/0331

Abstract: A fractional-N frequency synthesizer that suppresses integer boundary spurs. A frequency synthesizer includes a fractional-N phase locked loop (PLL) and a reference frequency scaler. The reference frequency scaler is coupled to a reference clock input of the PLL, the reference frequency scaler includes a programmable frequency divider, and a programmable frequency multiplier connected in series with the programmable frequency divider. Each of the divider and multiplier is configured to scale a reference frequency provided to the PLL by a programmable integer value.

Abstract translation: 一个抑制整数边界杂散的分数N频率合成器。 频率合成器包括分数N锁相环（PLL）和参考频率缩放器。 参考频率缩放器耦合到PLL的参考时钟输入，参考频率缩放器包括可编程分频器和与可编程分频器串联连接的可编程倍频器。 分频器和乘法器中的每一个被配置为通过可编程整数值来缩放提供给PLL的参考频率。