公开(公告)号：US20150287716A1

公开(公告)日：2015-10-08

申请号：US14245099

申请日：2014-04-04

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. Babcock ,  Alexei Sadovnikov

IPC: H01L27/082 ,  H01L29/04 ,  H01L29/16 ,  H01L21/265 ,  H01L21/8228 ,  H01L21/762 ,  H01L21/306 ,  H01L21/308 ,  H01L29/08 ,  H01L29/06 ,  H01L21/266

CPC classification number: H01L29/063 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/8228 ,  H01L21/82285 ,  H01L27/082 ,  H01L27/0826 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/732

Abstract: Complementary high-voltage bipolar transistors formed in standard bulk silicon integrated circuits are disclosed. In one disclosed embodiment, collector regions are formed in an epitaxial silicon layer. Base regions and emitters are disposed over the collector region. An n-type region is formed under collector region by implanting donor impurities into a p-substrate for the PNP transistor and implanting acceptor impurities into the p-substrate for the NPN transistor prior to depositing the collector epitaxial regions. Later in the process flow these n-type and p-type regions are connected to the top of the die by a deep n+ and p+ wells respectively. The n-type well is then coupled to VCC while the p-type well is coupled to GND, providing laterally depleted portions of the PNP and NPN collector regions and hence, increasing their BVs.

Abstract translation: 公开了在标准体硅集成电路中形成的互补高电压双极晶体管。 在一个公开的实施例中，集电极区域形成在外延硅层中。 基极区域和发射极设置在集电极区域上。 通过将供体杂质注入用于PNP晶体管的p衬底中并在沉积集电极外延区之前将受体杂质注入到NPN晶体管的p衬底中，在集电极区域形成n型区域。 在工艺流程中，这些n型和p型区域分别通过深n +和p +阱连接到管芯的顶部。 然后将n型阱耦合到VCC，而p型阱耦合到GND，提供PNP和NPN集电极区域的横向耗尽部分，并因此增加其BV。

公开(公告)号：US20200227440A1

公开(公告)日：2020-07-16

申请号：US16829970

申请日：2020-03-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexei Sadovnikov ,  Jeffrey A. Babcock

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L27/082 ,  H01L29/66 ,  H01L29/732 ,  H01L29/10 ,  H01L23/535 ,  H01L29/735

Abstract: Complementary high-voltage bipolar transistors in silicon-on-insulator (SC) integrated circuits is disclosed. In one disclosed embodiment, a collector region is formed in an epitaxial silicon layer disposed over a buried insulator layer. A base region and an emitter are disposed over the collector region. An n-type region is formed under the buried insulator layer (BOX) by implanting donor impurity through the active region of substrate and BOX into a p-substrate. Later in the process flow this n-type region is connected from the top by doped poly-silicon plug and is biased at Vcc. In this case it will deplete lateral portion of PNP collector region and hence, will increase its BV.

公开(公告)号：US20170194352A1

公开(公告)日：2017-07-06

申请号：US15464426

申请日：2017-03-21

Applicant: Texas Instruments Incorporated

Inventor： Alexei Sadovnikov ,  Jeffrey A. Babcock

IPC: H01L27/12 ,  H01L23/535 ,  H01L27/082 ,  H01L29/10 ,  H01L29/735 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L27/1203 ,  H01L23/535 ,  H01L27/082 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/10 ,  H01L29/1008 ,  H01L29/66265 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/735

Abstract: Complementary high-voltage bipolar transistors in silicon-on-insulator (SOl) integrated circuits is disclosed. In one disclosed embodiment, a collector region is formed in an epitaxial silicon layer disposed over a buried insulator layer. A base region and an emitter are disposed over the collector region. An n-type region is formed under the buried insulator layer (BOX) by implanting donor impurity through the active region of substrate and BOX into a p-substrate. Later in the process flow this n-type region is connected from the top by doped poly-silicon plug and is biased at Vcc. In this case it will deplete lateral portion of PNP collector region and hence, will increase its BV.

公开(公告)号：US09633995B2

公开(公告)日：2017-04-25

申请号：US15050808

申请日：2016-02-23

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. Babcock ,  Alexei Sadovnikov

IPC: H01L21/8249 ,  H01L27/06 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/423 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/45 ,  H01L29/49

CPC classification number: H01L27/0623 ,  H01L21/32139 ,  H01L21/8249 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/423 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66553 ,  H01L29/66575 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/66712 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7824 ,  H01L29/7835

Abstract: A method of fabricating a MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since the shield is composed of bipolar base material commonly used in SiGe BICMOS technologies.

公开(公告)号：US20160172355A1

公开(公告)日：2016-06-16

申请号：US15050684

申请日：2016-02-23

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. Babcock ,  Alexei Sadovnikov

IPC: H01L27/06 ,  H01L29/40 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0623 ,  H01L21/32139 ,  H01L21/8249 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/423 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66553 ,  H01L29/66575 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/66712 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7824 ,  H01L29/7835

Abstract: A method of fabricating a MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since the shield is composed of bipolar base material commonly used in SiGe BICMOS technologies.

Abstract translation: 一种以SiGe BICMOS技术制造MOSFET晶体管的方法，其结构在栅电极和漏极区之间形成漏极 - 栅极反馈电容屏蔽。 屏蔽不与栅极重叠，从而最小化对晶体管的输入电容的影响。 该过程不需要复杂或昂贵的处理，因为屏蔽由SiGe BICMOS技术中通常使用的双极母材组成。

公开(公告)号：US09343459B2

公开(公告)日：2016-05-17

申请号：US14245099

申请日：2014-04-04

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. Babcock ,  Alexei Sadovnikov

IPC: H01L21/8238 ,  H01L27/082 ,  H01L29/06 ,  H01L29/04 ,  H01L29/16 ,  H01L21/265 ,  H01L21/266 ,  H01L21/762 ,  H01L21/306 ,  H01L21/308 ,  H01L29/08 ,  H01L21/8228

CPC classification number: H01L29/063 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/8228 ,  H01L21/82285 ,  H01L27/082 ,  H01L27/0826 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/732

Abstract: Complementary high-voltage bipolar transistors formed in standard bulk silicon integrated circuits are disclosed. In one disclosed embodiment, collector regions are formed in an epitaxial silicon layer. Base regions and emitters are disposed over the collector region. An n-type region is formed under collector region by implanting donor impurities into a p-substrate for the PNP transistor and implanting acceptor impurities into the p-substrate for the NPN transistor prior to depositing the collector epitaxial regions. Later in the process flow these n-type and p-type regions are connected to the top of the die by a deep n+ and p+ wells respectively. The n-type well is then coupled to VCC while the p-type well is coupled to GND, providing laterally depleted portions of the PNP and NPN collector regions and hence, increasing their BVs.

Abstract translation: 公开了在标准体硅集成电路中形成的互补高电压双极晶体管。 在一个公开的实施例中，集电极区域形成在外延硅层中。 基极区域和发射极设置在集电极区域上。 通过将供体杂质注入用于PNP晶体管的p衬底中并在沉积集电极外延区之前将受体杂质注入到NPN晶体管的p衬底中，在集电极区域形成n型区域。 在工艺流程中，这些n型和p型区域分别通过深n +和p +阱连接到管芯的顶部。 然后将n型阱耦合到VCC，而p型阱耦合到GND，提供PNP和NPN集电极区域的横向耗尽部分，并因此增加其BV。

公开(公告)号：US20150270335A1

公开(公告)日：2015-09-24

申请号：US14219760

申请日：2014-03-19

Applicant: Texas Instruments Incorporated

Inventor： Alexei Sadovnikov ,  Jeffrey A. Babcock

IPC: H01L29/06 ,  H01L27/082 ,  H01L29/45 ,  H01L27/12 ,  H01L29/08

CPC classification number: H01L27/1203 ,  H01L23/535 ,  H01L27/082 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/10 ,  H01L29/1008 ,  H01L29/66265 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/735

Abstract: Complementary high-voltage bipolar transistors in silicon-on-insulator (SOI) integrated circuits is disclosed. In one disclosed embodiment, a collector region is formed in an epitaxial silicon layer disposed over a buried insulator layer. A base region and an emitter are disposed over the collector region. An n-type region is formed under the buried insulator layer (BOX) by implanting donor impurity through the active region of substrate and BOX into a p-substrate. Later in the process flow this n-type region is connected from the top by doped poly-silicon plug and is biased at Vcc. In this case it will deplete lateral portion of PNP collector region and hence, will increase its BV.

Abstract translation: 公开了绝缘体上硅（SOI）集成电路中的互补高压双极晶体管。 在一个公开的实施例中，集电极区域形成在设置在掩埋绝缘体层上的外延硅层中。 基极区域和发射极设置在集电极区域上方。 通过将施主杂质通过衬底和BOX的有源区注入到p衬底中，在掩埋绝缘体层（BOX）下方形成n型区域。 在该过程流程中，该n型区域从顶部通过掺杂的多晶硅插头连接并且被偏置在Vcc。 在这种情况下，它将消耗PNP集电极区域的侧面部分，因此将增加其BV。