Increasing efficiency of a switched mode power converter

    公开(公告)号:US10425000B2

    公开(公告)日:2019-09-24

    申请号:US15682094

    申请日:2017-08-21

    Abstract: Methods and apparatus to increase efficiency of a power converter using a bias voltage on a low side drive gate are disclosed. An example power converter includes an inductor; a transistor coupled to the inductor; and a driver coupled to a gate of the transistor, the driver to apply (A) a first voltage to the gate to enable the transistor, (B) a second voltage to the gate to disable the transistor, and (C) a third voltage to the gate during a transition between applying the first voltage and the second voltage, the third voltage being between the first voltage and the second voltage.

    Multiphase DC-To-DC Switching Power Converter with Leading Edge and Cross Channel Blanking
    15.
    发明申请
    Multiphase DC-To-DC Switching Power Converter with Leading Edge and Cross Channel Blanking 审中-公开
    具有前沿和交叉通道消隐的多相直流到直流开关电源转换器

    公开(公告)号:US20160294287A1

    公开(公告)日:2016-10-06

    申请号:US15180565

    申请日:2016-06-13

    CPC classification number: H02M1/08 H02M3/1584 H02M2001/0009

    Abstract: A multiphase DC-to-DC synchronous power converter, which has a number of converter channels that generate a corresponding number of current sense signals, blanks the current sense signals in a first converter channel for periods of time that correspond with the actions of the transistors in a second converter channel, where the actions result in noise spikes across the converter that falsely interfere with current sensing in the first converter channel.

    Abstract translation: 具有产生相应数量的电流感测信号的多个转换器通道的多相DC-DC同步电力转换器将第一转换器通道中的电流检测信号空白,以对应于晶体管的动作 在第二转换器通道中,其中的动作导致转换器上的噪声尖峰误差地干扰第一转换器通道中的电流感测。

    Switching regulator with configurable snubber

    公开(公告)号:US12027978B2

    公开(公告)日:2024-07-02

    申请号:US17828259

    申请日:2022-05-31

    CPC classification number: H02M3/158 H02M1/08 H02M1/344

    Abstract: A switching regulator includes a low-side switching transistor, a snubber transistor, a first pull-down transistor, and a second pull-down transistor. The low-side switching transistor includes a first current terminal and a second current terminal. The first current terminal is coupled to a switching node. The second current terminal is coupled to a ground terminal. The snubber transistor includes a first current terminal, a second current terminal, and a control terminal. The first current terminal is coupled to the switching node. The second current terminal is coupled to the ground terminal. The first pull-down transistor is coupled between the control terminal of the snubber transistor and the ground terminal. The second pull-down transistor is coupled between the control terminal of the snubber transistor and the ground terminal.

    Series capacitor buck converter having circuitry for precharging the series capacitor

    公开(公告)号:US11211865B2

    公开(公告)日:2021-12-28

    申请号:US16799112

    申请日:2020-02-24

    Abstract: A series capacitor buck converter includes a first half-bridge circuit including a first high side power switch (HSA) and first low side power switch (LSA) connected in series having a first switching node (SWA) therebetween which drives a first output inductor, a second half-bridge circuit including a second HS power switch (HSB) and second LS power switch (LSB) connected in series having a second switching node (SWB) therebetween which drives a second output inductor. A transfer capacitor (Ct) is connected in series with HSA and LSA and between the first and second half-bridge circuits. A first current source is coupled for precharging Ct with a charging current (I_in) and a second current source is coupled to Ct for providing an output current (I_out). A feedback network providing negative feedback forces I_out to match I_in.

    Balanced auxiliary on time generator for multiphase stackable constant on time control architecture
    18.
    发明授权
    Balanced auxiliary on time generator for multiphase stackable constant on time control architecture 有权
    平衡辅助时间发生器,用于多相可堆叠恒定的时间控制架构

    公开(公告)号:US08810294B2

    公开(公告)日:2014-08-19

    申请号:US14051346

    申请日:2013-10-10

    CPC classification number: H03K5/086

    Abstract: A control circuit configured to control a switching power supply including a ramp generator configured to generate a triangular waveform. A comparator is configured to generate a series of pulse width modulated (PWM) pulses at a first frequency and to regulate the switching power supply. The ramp generator includes a capacitor, a charging current source configured to provide a charging current to charge the capacitor, and a discharging current source configured to provide a discharging current to discharge the capacitor. The ramp generator also includes a closed loop current balancing current source configured to balance the currents from the charging and discharging current sources to establish a substantially zero direct current (DC) bias across the capacitor. The controller also includes a multi-phase configuration to provide a stackable multi-channel architecture.

    Abstract translation: 一种控制电路,被配置为控制包括被配置为产生三角形波形的斜坡发生器的开关电源。 比较器被配置为以第一频率产生一系列脉冲宽度调制(PWM)脉冲并且调节开关电源。 斜坡发生器包括电容器,被配置为提供充电电流以对电容器充电的充电电流源以及被​​配置为提供放电电流以对电容器放电的放电电流源。 斜坡发生器还包括闭环电流平衡电流源,其被配置为平衡来自充电和放电电流源的电流,以在电容器两端建立基本为零的直流(DC)偏置。 控制器还包括多相配置,以提供可堆叠的多通道架构。

    METHODS AND APPARATUS TO ADJUST A TRANSIENT RESPONSE

    公开(公告)号:US20200227913A1

    公开(公告)日:2020-07-16

    申请号:US16399576

    申请日:2019-04-30

    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to adjust a transient response. An example apparatus includes a clamping circuit including a first input, a second input, a third input, and an output, wherein the first input is adapted to be coupled to a selector, a reference voltage generator including an output, wherein the output of the reference voltage generator is coupled to the second input of the clamping circuit, an error amplifying circuit including an output, wherein the output of the error amplifying circuit is coupled to the third input of the clamping circuit, and a pulse width modulator including an input, wherein the input of the pulse width modulator is coupled to the output of the clamping circuit.

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