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公开(公告)号：US10425000B2
公开(公告)日：2019-09-24
申请号：US15682094
申请日：2017-08-21
摘要： Methods and apparatus to increase efficiency of a power converter using a bias voltage on a low side drive gate are disclosed. An example power converter includes an inductor; a transistor coupled to the inductor; and a driver coupled to a gate of the transistor, the driver to apply (A) a first voltage to the gate to enable the transistor, (B) a second voltage to the gate to disable the transistor, and (C) a third voltage to the gate during a transition between applying the first voltage and the second voltage, the third voltage being between the first voltage and the second voltage.
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公开(公告)号：US20190058394A1
公开(公告)日：2019-02-21
申请号：US15682094
申请日：2017-08-21
CPC分类号： H02M1/08 , H02M3/156 , H02M3/158 , H03K17/165 , H03K2217/0036 , H03K2217/0063 , H03K2217/0072
摘要： Methods and apparatus to increase efficiency of a power converter using a bias voltage on a low side drive gate are disclosed. An example power converter includes an inductor; a transistor coupled to the inductor; and a driver coupled to a gate of the transistor, the driver to apply (A) a first voltage to the gate to enable the transistor, (B) a second voltage to the gate to disable the transistor, and (C) a third voltage to the gate during a transition between applying the first voltage and the second voltage, the third voltage being between the first voltage and the second voltage.
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公开(公告)号：US10727730B2
公开(公告)日：2020-07-28
申请号：US16529227
申请日：2019-08-01
摘要： Methods and apparatus to increase efficiency of a power converter using a bias voltage on a low side drive gate are disclosed. An example power converter includes an inductor; a transistor coupled to the inductor; and a driver coupled to a gate of the transistor, the driver to apply (A) a first voltage to the gate to enable the transistor, (B) a second voltage to the gate to disable the transistor, and (C) a third voltage to the gate during a transition between applying the first voltage and the second voltage, the third voltage being between the first voltage and the second voltage.
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公开(公告)号：US10529796B2
公开(公告)日：2020-01-07
申请号：US16178352
申请日：2018-11-01
IPC分类号： H01L49/02 , H01L23/66 , H01L23/495
摘要： A galvanic isolation device includes a first integrated circuit (IC) die that has communication circuitry formed in a circuit layer below the top surface. A first conductive plate is formed on the IC die proximate the top surface, and is coupled to the communication circuitry. A dielectric isolation layer is formed over a portion of the top surface of the IC after the IC is fabricated such that the dielectric isolation layer completely covers the conductive plate. A second conductive plate is juxtaposed with the first conductive plate but separated by the dielectric isolation layer such that the first conductive plate and the second conductive plate form a capacitor. The second conductive plate is configured to be coupled to a second communication circuit.
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公开(公告)号：US20190006338A1
公开(公告)日：2019-01-03
申请号：US16126577
申请日：2018-09-10
IPC分类号： H01L25/16 , H04B10/80 , H01L31/103 , H01L23/31 , H01L23/49 , H01L23/495 , H01L23/00 , H01L33/62 , H01L33/00 , H01L31/167 , H01L31/11 , H01F38/14 , H01L31/101 , H01L31/0203 , H01L31/02 , H01L49/02
摘要： In described examples, an integrated circuit includes a leadframe structure, which includes electrical conductors. A first coil structure is electrically connected to a first pair of the electrical conductors of the leadframe structure. The first coil structure is partially formed on a semiconductor die structure. A second coil structure is electrically connected to a second pair of the electrical conductors of the leadframe structure. The second coil structure is partially formed on the semiconductor die structure. A molded package structure encloses portions of the leadframe structure. The molded package structure exposes portions of the first and second pairs of the electrical conductors to allow external connection to the first and second coil structures. The molded package structure includes a cavity to magnetically couple portions of the first and second coil structures.
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公开(公告)号：US20180162722A1
公开(公告)日：2018-06-14
申请号：US15372565
申请日：2016-12-08
CPC分类号： B81B7/0048 , B81B7/0061 , B81B2201/0264 , B81C1/00325
摘要： Disclosed examples include sensor apparatus and integrated circuits having a package structure with an internal cavity and an opening that connects of the cavity with an ambient condition of an exterior of the package structure, and an electronic sensor structure mechanically supported by wires in the cavity and including a sensing surface exposed to the cavity to sense the ambient condition of an exterior of the package structure.
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公开(公告)号：US09929110B1
公开(公告)日：2018-03-27
申请号：US15395456
申请日：2016-12-30
CPC分类号： H01L23/66 , G02B3/08 , G02B19/0014 , G02B19/0076 , G02B27/0955 , G02B27/0977 , H01L21/56 , H01L23/3121 , H01L33/54
摘要： A method of forming, and a resulting, an integrated circuit wave device. The method (i) affixes an integrated circuit die relative to a substrate; (ii) creates a form relative to the integrated circuit die and the substrate; and (iii) forms a wave shaping member having a shape conforming at least in part to a shape of the form.
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公开(公告)号：US11264369B2
公开(公告)日：2022-03-01
申请号：US16859345
申请日：2020-04-27
IPC分类号： H01L25/16 , H01F38/14 , H01L31/0203 , H01L31/101 , H01L23/31 , H01L23/49 , H01L23/495 , H01L49/02 , H01L31/02 , H01L31/103 , H01L31/11 , H01L31/167 , H01L33/62 , H04B10/80 , H01L33/00 , H01L33/60 , H01L23/00
摘要： In described examples, an integrated circuit includes a leadframe structure, which includes electrical conductors. A first coil structure is electrically connected to a first pair of the electrical conductors of the leadframe structure. The first coil structure is partially formed on a semiconductor die structure. A second coil structure is electrically connected to a second pair of the electrical conductors of the leadframe structure. The second coil structure is partially formed on the semiconductor die structure. A molded package structure encloses portions of the leadframe structure. The molded package structure exposes portions of the first and second pairs of the electrical conductors to allow external connection to the first and second coil structures. The molded package structure includes a cavity to magnetically couple portions of the first and second coil structures.
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公开(公告)号：US20200258874A1
公开(公告)日：2020-08-13
申请号：US16859345
申请日：2020-04-27
IPC分类号： H01L25/16 , H01L33/00 , H04B10/80 , H01L33/62 , H01L31/167 , H01L31/11 , H01L31/103 , H01L31/02 , H01L49/02 , H01L23/495 , H01L23/49 , H01L23/31 , H01F38/14 , H01L31/101 , H01L31/0203
摘要： In described examples, an integrated circuit includes a leadframe structure, which includes electrical conductors. A first coil structure is electrically connected to a first pair of the electrical conductors of the leadframe structure. The first coil structure is partially formed on a semiconductor die structure. A second coil structure is electrically connected to a second pair of the electrical conductors of the leadframe structure. The second coil structure is partially formed on the semiconductor die structure. A molded package structure encloses portions of the leadframe structure. The molded package structure exposes portions of the first and second pairs of the electrical conductors to allow external connection to the first and second coil structures. The molded package structure includes a cavity to magnetically couple portions of the first and second coil structures.
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公开(公告)号：US20190356212A1
公开(公告)日：2019-11-21
申请号：US16529227
申请日：2019-08-01
摘要： Methods and apparatus to increase efficiency of a power converter using a bias voltage on a low side drive gate are disclosed. An example power converter includes an inductor; a transistor coupled to the inductor; and a driver coupled to a gate of the transistor, the driver to apply (A) a first voltage to the gate to enable the transistor, (B) a second voltage to the gate to disable the transistor, and (C) a third voltage to the gate during a transition between applying the first voltage and the second voltage, the third voltage being between the first voltage and the second voltage.
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