公开(公告)号：US11086778B2

公开(公告)日：2021-08-10

申请号：US16601813

申请日：2019-10-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai Chirca ,  Timothy David Anderson ,  Joseph Zbiciak ,  David E. Smith ,  Matthew David Pierson

IPC: G06F12/0817 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/0875 ,  G06F12/10 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0855 ,  G06F12/06 ,  G06F12/0831 ,  G06F13/12 ,  G06F3/06 ,  G06F12/0815 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/0891

Abstract: Techniques for accessing memory by a memory controller, comprising receiving, by the memory controller, a memory management command to perform a memory management operation at a virtual memory address, translating the virtual memory address to a physical memory address, wherein the physical memory address comprises an address within a cache memory, and outputting an instruction to the cache memory based on the memory management command and the physical memory address.

公开(公告)号：US11080047B2

公开(公告)日：2021-08-03

申请号：US16018234

申请日：2018-06-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Due Quang Bui ,  Mel Alan Phipps ,  Todd T. Hahn ,  Joseph Zbiciak

IPC: G06F9/30

Abstract: The number of registers required is reduced by overlapping scalar and vector registers. This allows increased compiler flexibility when mixing scalar and vector instructions. Local register read ports are reduced by restricting read access. Dedicated predicate registers reduce requirements for general registers, and allows reduction of critical timing paths by allowing the predicate registers to be placed next to the predicate unit.

公开(公告)号：US20210133106A1

公开(公告)日：2021-05-06

申请号：US17146576

申请日：2021-01-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F12/0815 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F12/0862

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template specifies loop count and loop dimension for each nested loop. A format definition field in the stream template specifies the number of loops and the stream template bits devoted to the loop counts and loop dimensions. This permits the same bits of the stream template to be interpreted differently enabling trade off between the number of loops supported and the size of the loop counts and loop dimensions.

公开(公告)号：US10990398B2

公开(公告)日：2021-04-27

申请号：US16384434

申请日：2019-04-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Kai Chirca

IPC: G06F9/38 ,  G06F11/00 ,  G06F12/0897 ,  G06F9/30 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0875 ,  G06F9/345

Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, beginning execution of the first instruction, receiving one or more second instructions for execution on the instruction execution pipeline, the one or more second instructions associated with a higher priority task than the first instruction, storing a register state associated with the execution of the first instruction in one or more registers of a capture queue associated with the instruction execution pipeline, copying the register state from the capture queue to a memory, determining that the one or more second instructions have been executed, copying the register state from the memory to the one or more registers of the capture queue, and restoring the register state to the instruction execution pipeline from the capture queue.

公开(公告)号：US10983912B2

公开(公告)日：2021-04-20

申请号：US16423813

申请日：2019-05-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F9/35 ,  G06F12/0862 ,  G06F9/345 ,  G06F9/355 ,  G06F9/38 ,  G06F12/02

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template register specifies a circular address mode for the loop, first and second block size numbers and a circular address block size selection. For a first circular address block size selection the block size corresponds to the first block size number. For a first circular address block size selection the block size corresponds to the first block size number. For a second circular address block size selection the block size corresponds to a sum of the first block size number and the second block size number.

公开(公告)号：US10891231B2

公开(公告)日：2021-01-12

申请号：US16459210

申请日：2019-07-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F9/40 ,  G06F12/00 ,  G06F15/76 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F12/0862 ,  G06F15/80 ,  G06F9/32

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template specifies loop count and loop dimension for each nested loop. A format definition field in the stream template specifies the number of loops and the stream template bits devoted to the loop counts and loop dimensions. This permits the same bits of the stream template to be interpreted differently enabling trade off between the number of loops supported and the size of the loop counts and loop dimensions.

公开(公告)号：US20200341760A1

公开(公告)日：2020-10-29

申请号：US16871253

申请日：2020-05-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/345

Abstract: A streaming engine employed in a digital signal processor specified a fixed data stream. Once started the data stream is read only and cannot be written. Once fetched, the data stream is stored in a first-in-first-out buffer for presentation to functional units in the fixed order. Data use by the functional unit is controlled using the input operand fields of the corresponding instruction. A read only operand coding supplies the data an input of the functional unit. A read/advance operand coding supplies the data and also advances the stream to the next sequential data elements. The read only operand coding permits reuse of data without requiring a register of the register file for temporary storage.

公开(公告)号：US10768933B2

公开(公告)日：2020-09-08

申请号：US16273413

申请日：2019-02-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy D. Anderson

IPC: G06F9/34 ,  G06F12/08 ,  G06F13/14 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/10

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces addresses of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. Stream metadata is stored in response to a stream store instruction. Stored stream metadata is restored to the stream engine in response to a stream restore instruction. An interrupt changes an open stream to a frozen state discarding stored stream data. A return from interrupt changes a frozen stream to an active state.

公开(公告)号：US20200091943A1

公开(公告)日：2020-03-19

申请号：US16694205

申请日：2019-11-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dheera Balasubramanian ,  Joseph Zbiciak ,  Duc Quang Bui ,  Timothy David Anderson

IPC: H03M13/00 ,  H03M13/27 ,  G06F9/38

Abstract: A method is shown that is operable to transform and align a plurality of fields from an input to an output data stream using a multilayer butterfly or inverse butterfly network. Many transformations are possible with such a network which may include separate control of each multiplexer. This invention supports a limited set of multiplexer control signals, which enables a similarly limited set of data transformations. This limited capability is offset by the reduced complexity of the multiplexor control circuits.

公开(公告)号：US20190391918A1

公开(公告)日：2019-12-26

申请号：US16459210

申请日：2019-07-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F12/0815 ,  G06F9/38 ,  G06F9/345 ,  G06F9/30 ,  G06F12/0897 ,  G06F12/0875

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template specifies loop count and loop dimension for each nested loop. A format definition field in the stream template specifies the number of loops and the stream template bits devoted to the loop counts and loop dimensions. This permits the same bits of the stream template to be interpreted differently enabling trade off between the number of loops supported and the size of the loop counts and loop dimensions.