公开(公告)号：US12235705B2

公开(公告)日：2025-02-25

申请号：US18534911

申请日：2023-12-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mustafa Ulvi Erdogan ,  Suzanne Mary Vining ,  Bharath Kumar Singareddy ,  Douglas Edward Wente

IPC: G06F1/3215 ,  G06F1/3234 ,  G06F13/38 ,  G06F13/42

Abstract: High-speed data communication devices, e.g., repeaters, interfacing between a host and a peripheral operate such that high-speed components except for a host-side squelch detector are set or maintained in a deactivated state during an idle period of a micro frame. In an example, a start of a micro frame is detected on a data bus during a first time period. In a second time period after the first time period, the high-speed communication device determines whether at least one data packet is contained in the micro frame. When it is determined during the second time period that no data packet is contained in the micro frame, active components, except a squelch detector, are controlled to be inactive during a third time period after the second time period.

公开(公告)号：US11792361B2

公开(公告)日：2023-10-17

申请号：US17363158

申请日：2021-06-30

Applicant: Texas Instruments Incorporated

Inventor： Charles Michael Campbell ,  Mustafa Ulvi Erdogan ,  Douglas Edward Wente ,  Sridhar Ramaswamy

IPC: H04N7/10 ,  H04N21/442 ,  H04N21/4363

CPC classification number: H04N7/102 ,  H04N21/43635 ,  H04N21/44227

Abstract: A redriver system adapted for coupling to a first device and to a second device includes first and second transmitter drivers and a snoop circuit. The first transmitter driver has a first enable input. The second transmitter driver has a second enable input. The snoop circuit is coupled to the first and second enable inputs. The snoop circuit is configured to determine whether the first device and the second device are to operate according to a first protocol. Responsive to the snoop circuit determining that the first and second devices are to operate according to the first protocol, the snoop circuit enables the first transmitter driver and disables the second transmitter driver. Responsive to the snoop circuit determining that the first and second devices are not to operate according to the first protocol, the snoop circuit disables the first transmitter driver and enables the second transmitter driver.

公开(公告)号：US20220206556A1

公开(公告)日：2022-06-30

申请号：US17330027

申请日：2021-05-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mustafa Ulvi Erdogan ,  Suzanne Mary Vining ,  Bharath Kumar Singareddy ,  Douglas Edward Wente

IPC: G06F1/3215 ,  G06F13/42 ,  G06F1/3234 ,  G06F13/38

Abstract: High-speed data communication devices, e.g., repeaters, interfacing between a host and a peripheral operate such that high-speed components except for a host-side squelch detector are set or maintained in a deactivated state during an idle period of a micro frame. In an example, a start of a micro frame is detected on a data bus during a first time period. In a second time period after the first time period, the high-speed communication device determines whether at least one data packet is contained in the micro frame. When it is determined during the second time period that no data packet is contained in the micro frame, active components, except a squelch detector, are controlled to be inactive during a third time period after the second time period.

公开(公告)号：US10762016B2

公开(公告)日：2020-09-01

申请号：US16404494

申请日：2019-05-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Win Naing Maung ,  Douglas Edward Wente ,  Mustafa Ulvi Erdogan ,  Huanzhang Huang ,  Saurabh Goyal ,  Bhupendra Sharma

IPC: G06F13/38 ,  G06F13/42 ,  H04B3/36

Abstract: Aspects of the disclosure provide for a circuit including a squelch detector having a first input coupled to a first node and configured to receive a positive component of a differential signal with a floating center tap, a second input coupled to a second node and configured to receive a negative component of the differential signal, and an output coupled to a logic circuit, a first resistor coupled between the first node and a third node, a second resistor coupled between the third node and the second node, a third resistor coupled between the first node and a fourth node, a fourth resistor coupled between the fourth node and the second node, a capacitor coupled between the fourth node and a ground terminal, a comparator having a first input coupled to the third node, a second input coupled to a fifth node, and an output coupled to the logic circuit.

公开(公告)号：US20240103595A1

公开(公告)日：2024-03-28

申请号：US18534911

申请日：2023-12-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mustafa Ulvi Erdogan ,  Suzanne Mary Vining ,  Bharath Kumar Singareddy ,  Douglas Edward Wente

IPC: G06F1/3215 ,  G06F1/3234 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F1/3215 ,  G06F1/3253 ,  G06F13/385 ,  G06F13/4282 ,  G06F2213/0042

Abstract: High-speed data communication devices, e.g., repeaters, interfacing between a host and a peripheral operate such that high-speed components except for a host-side squelch detector are set or maintained in a deactivated state during an idle period of a micro frame. In an example, a start of a micro frame is detected on a data bus during a first time period. In a second time period after the first time period, the high-speed communication device determines whether at least one data packet is contained in the micro frame. When it is determined during the second time period that no data packet is contained in the micro frame, active components, except a squelch detector, are controlled to be inactive during a third time period after the second time period.

公开(公告)号：US11874718B2

公开(公告)日：2024-01-16

申请号：US17330027

申请日：2021-05-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mustafa Ulvi Erdogan ,  Suzanne Mary Vining ,  Bharath Kumar Singareddy ,  Douglas Edward Wente

IPC: G06F1/3215 ,  G06F13/42 ,  G06F13/38 ,  G06F1/3234

CPC classification number: G06F1/3215 ,  G06F1/3253 ,  G06F13/385 ,  G06F13/4282 ,  G06F2213/0042

Abstract: High-speed data communication devices, e.g., repeaters, interfacing between a host and a peripheral operate such that high-speed components except for a host-side squelch detector are set or maintained in a deactivated state during an idle period of a micro frame. In an example, a start of a micro frame is detected on a data bus during a first time period. In a second time period after the first time period, the high-speed communication device determines whether at least one data packet is contained in the micro frame. When it is determined during the second time period that no data packet is contained in the micro frame, active components, except a squelch detector, are controlled to be inactive during a third time period after the second time period.

公开(公告)号：US11386036B2

公开(公告)日：2022-07-12

申请号：US16404461

申请日：2019-05-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Win Naing Maung ,  Saurabh Goyal ,  Bhupendra Sharma ,  Huanzhang Huang ,  Douglas Edward Wente ,  Suzanne Mary Vining ,  Mustafa Ulvi Erdogan

IPC: G06F13/42 ,  G06F13/38 ,  H04L12/46 ,  H03F3/45 ,  H04B3/58

Abstract: At least some aspects of the present disclosure provide for a method. In some examples, the method includes receiving, at a circuit, data via a differential input signal, detecting a rising edge in the data received via the differential input signal, and precharging a common mode voltage (Vcm) node of the differential input signal responsive to detecting the rising edge in the data received via the differential input signal, wherein the Vcm node is a floating node.

公开(公告)号：US11153135B1

公开(公告)日：2021-10-19

申请号：US17146454

申请日：2021-01-11

Applicant: Texas Instruments Incorporated

Inventor： Shita Guo ,  Yanli Fan ,  Mustafa Ulvi Erdogan ,  Douglas Edward Wente

IPC: H04L25/03

Abstract: Methods and systems of adaptive equalization to compensate channel loss are disclosed. A method includes detecting a peak amplitude of an equalizer output signal and selecting a set of reference voltage levels from M sets based on the peak amplitude of the equalizer output signal, each of the M sets having N reference voltage levels. The method includes continuing to increase an equalization level in predetermined steps to a next higher equalization level if the applied equalization level does not correspond to the over-equalization level and evaluating the distribution of the resulting hit counts for each increase to the next higher equalization level until the applied equalization level corresponds to the over-equalization level. The method includes decreasing to the previously applied lower equalization level if the applied equalization level corresponds to the over-equalization level.

公开(公告)号：US10922255B2

公开(公告)日：2021-02-16

申请号：US16939725

申请日：2020-07-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Win Naing Maung ,  Douglas Edward Wente ,  Mustafa Ulvi Erdogan ,  Huanzhang Huang ,  Saurabh Goyal ,  Bhupendra Sharma

IPC: G06F13/42 ,  G06F13/38 ,  H04B3/36

Abstract: Aspects of the disclosure provide for a circuit including a squelch detector having a first input coupled to a first node and configured to receive a positive component of a differential signal with a floating center tap, a second input coupled to a second node and configured to receive a negative component of the differential signal, and an output coupled to a logic circuit, a first resistor coupled between the first node and a third node, a second resistor coupled between the third node and the second node, a third resistor coupled between the first node and a fourth node, a fourth resistor coupled between the fourth node and the second node, a capacitor coupled between the fourth node and a ground terminal, a comparator having a first input coupled to the third node, a second input coupled to a fifth node, and an output coupled to the logic circuit.

公开(公告)号：US09438253B2

公开(公告)日：2016-09-06

申请号：US14727990

申请日：2015-06-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mustafa Ulvi Erdogan

IPC: H03L7/08 ,  H03L7/087 ,  H04L7/00 ,  H03L7/089

CPC classification number: H03L7/0807 ,  H03L7/087 ,  H03L7/089 ,  H04L7/0045

Abstract: A current mode logic (CML) latch that includes a first transistor coupled to a second transistor, a third transistor coupled to a fourth transistor, a first capacitor connected to the first, second, third, and fourth transistors, and a second capacitor cross-coupled with the first capacitor and connected to the third and fourth transistors. The first and second transistors are configured to receive a data signal. The third and fourth transistors are configured to receive a clock signal.

Abstract translation: 电流模式逻辑（CML）锁存器，其包括耦合到第二晶体管的第一晶体管，耦合到第四晶体管的第三晶体管，连接到第一，第二，第三和第四晶体管的第一电容器， 与第一电容耦合并连接到第三和第四晶体管。 第一和第二晶体管被配置为接收数据信号。 第三和第四晶体管被配置为接收时钟信号。