公开(公告)号：US20200327950A1

公开(公告)日：2020-10-15

申请号：US16916911

申请日：2020-06-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aravind GANESAN ,  Jaiganesh BALAKRISHNAN ,  Nagarajan VISWANATHAN ,  Yeswanth GUNTUPALLI ,  Ajai PAULOSE ,  Mathews JOHN ,  Jagannathan VENKATARAMAN ,  Neeraj SHRIVASTAVA

IPC: G11C29/02 ,  G11C17/18 ,  G11C17/16 ,  G11C17/14

Abstract: A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.

公开(公告)号：US20200152284A1

公开(公告)日：2020-05-14

申请号：US16235698

申请日：2018-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aravind GANESAN ,  Jaiganesh BALAKRISHNAN ,  Nagarajan VISWANATHAN ,  Yeswanth GUNTUPALLI ,  Ajai PAULOSE ,  Mathews JOHN ,  Jagannathan VENKATARAMAN ,  Neeraj SHRIVASTAVA

IPC: G11C29/02 ,  G11C17/18 ,  G11C17/14 ,  G11C17/16

Abstract: A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.

公开(公告)号：US20190207617A1

公开(公告)日：2019-07-04

申请号：US16104978

申请日：2018-08-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ani XAVIER ,  Neeraj SHRIVASTAVA ,  Arun MOHAN

IPC: H03M1/12 ,  G06F1/04

CPC classification number: H03M1/1245 ,  G06F1/04 ,  G11C27/02

Abstract: In some examples, a system includes a first transistor comprising a first source terminal coupled to a first input terminal, a first drain terminal coupled to a first top plate sampling capacitor, and a first gate terminal. The system also includes a first input-dependent dual clock boost circuit coupled to the first input terminal via a first boost circuit input and to the first gate terminal via a first boost circuit output. The system further includes a second transistor comprising a second source terminal coupled to a second input terminal, a second drain terminal coupled to a second top plate sampling capacitor, and a second gate terminal. The system also includes a second input-dependent dual clock boost circuit coupled to the second input terminal via a second boost circuit input and to the second gate terminal of the second transistor via a second boost circuit output.

公开(公告)号：US20190013816A1

公开(公告)日：2019-01-10

申请号：US15859437

申请日：2017-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Neeraj SHRIVASTAVA ,  Jafar Sadique KAVILADATH

IPC: H03M1/00

Abstract: In some examples, a system comprises an analog-to-digital converter (ADC) to receive an analog input signal and a reset signal, the ADC to convert the analog input signal into a digital signal. The system comprises a digital-to-analog converter (DAC), coupled to the ADC, to convert the digital signal into an internal analog signal. The system includes a first capacitor, coupled to the DAC, to receive the internal analog signal. The system comprises a first switch, coupled to the first capacitor, to provide the analog input signal to the first capacitor. The system comprises a second switch to couple the first capacitor to ground.