公开(公告)号：US20190131870A1

公开(公告)日：2019-05-02

申请号：US16228191

申请日：2018-12-20

Applicant: Texas Instruments Incorporated

Inventor： Roy Alan Hastings

IPC: H02M3/07 ,  G05F1/46 ,  G05F3/24 ,  G05F1/575

CPC classification number: H02M3/07 ,  G05F1/468 ,  G05F1/575 ,  G05F3/247

Abstract: A reference signal generator includes a voltage reference, an amplifier coupled to the voltage reference, and a precharge circuit coupled to the amplifier. The voltage reference is configured to generate a constant voltage. The amplifier is configured to receive the constant voltage from the voltage reference and generate a regulating primary output signal and a non-regulating secondary output signal. The precharge circuit is configured to charge a noise reduction capacitor with the non-regulating secondary output signal.

公开(公告)号：US10199932B1

公开(公告)日：2019-02-05

申请号：US15730823

申请日：2017-10-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Roy Alan Hastings

IPC: H02M3/07 ,  G05F3/24 ,  G05F1/575 ,  G05F1/46

Abstract: A reference signal generator includes a voltage reference, an amplifier coupled to the voltage reference, and a precharge circuit coupled to the amplifier. The voltage reference is configured to generate a constant voltage. The amplifier is configured to receive the constant voltage from the voltage reference and generate a regulating primary output signal and a non-regulating secondary output signal. The precharge circuit is configured to charge a noise reduction capacitor with the non-regulating secondary output signal.

公开(公告)号：US12088286B2

公开(公告)日：2024-09-10

申请号：US17364206

申请日：2021-06-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chengxi Liu ,  Roy Alan Hastings

IPC: H03K17/14 ,  G01K7/01 ,  H01L21/8222 ,  H01L29/417 ,  H01L29/73 ,  G05F3/22 ,  G05F3/24

CPC classification number: H03K17/14 ,  G01K7/01 ,  H01L21/8222 ,  H01L29/41708 ,  G05F3/225 ,  G05F3/242 ,  H01L29/73

Abstract: In examples, a circuit comprises a first current source coupled to a voltage source node. The circuit comprises a resistor having a first resistor terminal and a second resistor terminal, where the first resistor terminal is coupled to the first current source. The circuit comprises a bipolar transistor having a base, a collector, and an emitter, with the base coupled to the first resistor terminal, the emitter coupled to the second resistor terminal, and the collector coupled to the voltage source node. The circuit comprises a second current source coupled to the emitter and the second resistor terminal, with the second current source coupled to a ground node. The circuit comprises a Schmitt trigger having an input coupled to the emitter, the second resistor terminal, and the second current source.

公开(公告)号：US11719728B2

公开(公告)日：2023-08-08

申请号：US17935260

申请日：2022-09-26

Applicant: Texas Instruments Incorporated

Inventor： Roy Alan Hastings

IPC: G01R19/00 ,  H01L27/02

CPC classification number: G01R19/0092 ,  H01L27/0207

Abstract: A sectioned field effect transistor (“FET”) for implementing a rapidly changing sense range ratio dynamically in response to changing load and main supply conditions. The sectioned FET may have multiple main FET sections, and multiple sense FET sections. These sections can be dynamically connected and disconnected from the sectioned FET. The sections may also be connected by a common gate. There may also be common drain or source connections for the main FET sections, and also common drain or source connections for the sense FET sections. The sectioned FET allows for the sense range to be extended by a multiple of k+1, where k is the size ratio or factor of the additional sense FET sections. This allows the current sense range ratio to be extended to (m+n)/n*(k+1).

公开(公告)号：US11486909B2

公开(公告)日：2022-11-01

申请号：US17077404

申请日：2020-10-22

Applicant: Texas Instruments Incorporated

Inventor： Roy Alan Hastings

IPC: G01R19/00 ,  H01L27/02

Abstract: A sectioned field effect transistor (“FET”) for implementing a rapidly changing sense range ratio dynamically in response to changing load and main supply conditions. The sectioned FET may have multiple main FET sections, and multiple sense FET sections. These sections can be dynamically connected and disconnected from the sectioned FET. The sections may also be connected by a common gate. There may also be common drain or source connections for the main FET sections, and also common drain or source connections for the sense FET sections. The sectioned FET allows for the sense range to be extended by a multiple of k+1, where k is the size ratio or factor of the additional sense FET sections. This allows the current sense range ratio to be extended to (m+n)/n*(k+1).

公开(公告)号：US11289245B2

公开(公告)日：2022-03-29

申请号：US16911039

申请日：2020-06-24

Applicant: Texas Instruments Incorporated

Inventor： Roy Alan Hastings

IPC: H01C1/16 ,  H03M1/38 ,  H03M1/66

Abstract: In an example, a device comprises a first resistor coupled to a second resistor and to a trim resistor, the second resistor and the trim resistor coupled to a port configured to couple to a third resistor. The device also comprises a comparator having an inverting input coupled to a first node between the second resistor and the port and a non-inverting input coupled to a second node between the first resistor and the trim resistor. The device further includes a trim control circuit coupled to an output of the comparator and having an output coupled to the trim resistor, the trim control circuit configured to couple to multiple integrated trim resistors external to the device.

公开(公告)号：US20200321149A1

公开(公告)日：2020-10-08

申请号：US16911039

申请日：2020-06-24

Applicant: Texas Instruments Incorporated

Inventor： Roy Alan Hastings

IPC: H01C1/16 ,  H03M1/38 ,  H03M1/66

Abstract: In an example, a device comprises a first resistor coupled to a second resistor and to a trim resistor, the second resistor and the trim resistor coupled to a port configured to couple to a third resistor. The device also comprises a comparator having an inverting input coupled to a first node between the second resistor and the port and a non-inverting input coupled to a second node between the first resistor and the trim resistor. The device further includes a trim control circuit coupled to an output of the comparator and having an output coupled to the trim resistor, the trim control circuit configured to couple to multiple integrated trim resistors external to the device.

公开(公告)号：US20200088770A1

公开(公告)日：2020-03-19

申请号：US16135625

申请日：2018-09-19

Applicant: Texas Instruments Incorporated

Inventor： Roy Alan Hastings

IPC: G01R19/00 ,  H01L27/02

Abstract: A sectioned field effect transistor (“FET”) for implementing a rapidly changing sense range ratio dynamically in response to changing load and main supply conditions. The sectioned FET may have multiple main FET sections, and multiple sense FET sections. These sections can be dynamically connected and disconnected from the sectioned FET. The sections may also be connected by a common gate. There may also be common drain or source connections for the main FET sections, and also common drain or source connections for the sense FET sections. The sectioned FET allows for the sense range to be extended by a multiple of k+1, where k is the size ratio or factor of the additional sense FET sections. This allows the current sense range ratio to be extended to (m+n)/n*(k+1).