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公开(公告)号:US10218324B2
公开(公告)日:2019-02-26
申请号:US15395073
申请日:2016-12-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Vadim Valerievich Ivanov , Srinivas K. Pulijala
IPC: H03F3/45
Abstract: At least some embodiments are directed to a system that comprises a differential input transistor pair (DITP) comprising first and second transistors, a first feedback loop coupled to the first transistor, and a second feedback loop coupled to the second transistor. When a differential voltage applied to the input stage is within a first range, the first and second feedback loops control a tail current supplied to the DITP, where the tail current at least partially determines a transconductance of the DITP. When the differential voltage is within a second range, the transconductance of the DITP is at least partially determined by a first resistor in the first feedback loop or by a second resistor in the second feedback loop.
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公开(公告)号:US10931247B2
公开(公告)日:2021-02-23
申请号:US16357572
申请日:2019-03-19
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: A chopper amplifier circuit includes a first amplifier path, a second amplifier path, and a third amplifier path. The first amplifier path includes chopper circuitry configured to modulate an input signal and an offset voltage at a chopping frequency, and ripple reduction circuitry configured to attenuate the chopping frequency in a signal in the first amplifier path. The second amplifier path includes a feedforward gain stage, and is configured to apply higher gain to intermediate signal frequencies than is applied in the first amplifier path. The third amplifier path includes a feedforward gain stage, and is configured to apply higher gain to high signal frequencies than is applied in the first amplifier path and the second amplifier path. The intermediate signal frequencies are lower than the high signal frequencies.
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公开(公告)号:US10511269B2
公开(公告)日:2019-12-17
申请号:US15995355
申请日:2018-06-01
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Bharath Karthik Vasan , Srinivas K. Pulijala , Steven G. Brantley
Abstract: A voltage-to-current converter that reduces third harmonic distortion. An amplifier includes an input stage. The input stage includes a first voltage-to-current conversion stage and a second voltage-to-current conversion stage. The first voltage-to-current conversion stage is configured to provide an input to output gain with compressive nonlinearity. The second voltage-to-current stage is cascaded with the first voltage-to-current conversion stage. An input of the second voltage-to-current stage is connected to an output of the first voltage-to-current conversion stage. The second voltage-to-current conversion stage is configured to provide an input to output gain with expansive nonlinearity.
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公开(公告)号:US10461706B1
公开(公告)日:2019-10-29
申请号:US15966946
申请日:2018-04-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Steven G. Brantley , Bharath Karthik Vasan , Srinivas K. Pulijala , Martijn Snoeij
Abstract: In examples, a system comprises a differential amplifier coupled to a parasitic capacitor positioned between a first node and a first reference voltage source. The system comprises a buffer amplifier having an input terminal and an output terminal, the input terminal coupled to the first node and the output terminal coupled to a cancellation capacitor. The system includes a controlled current source coupled to the first node and the input terminal, the controlled current source coupled to a second reference voltage source. The system comprises a current sense circuit coupled to the cancellation capacitor and the second reference voltage source.
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公开(公告)号:US20180145633A1
公开(公告)日:2018-05-24
申请号:US15876561
申请日:2018-01-22
Applicant: Texas Instruments Incorporated
Inventor: Srinivas K. Pulijala , Steven G. Brantley
CPC classification number: H03F1/02 , H03F1/14 , H03F3/20 , H03F2200/135 , H03F2200/153 , H03F2200/171 , H03F2200/297 , H03F2200/408
Abstract: An amplifier includes an amplifier input and an amplifier output. A compensation network is coupled to the amplifier output. The compensation network includes at least one RC network tuned to a frequency in which the amplifier operates. The compensation network provides at least one zero to compensate for at least one pole introduced by a load coupled to the amplifier output.
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公开(公告)号:US09595929B2
公开(公告)日:2017-03-14
申请号:US14508755
申请日:2014-10-07
Applicant: Texas Instruments Incorporated
Inventor: Srinivas K. Pulijala , Steven G. Brantley
CPC classification number: H03F1/02 , H03F1/14 , H03F3/20 , H03F2200/135 , H03F2200/153 , H03F2200/171 , H03F2200/297 , H03F2200/408
Abstract: An amplifier includes an amplifier input and an amplifier output. A compensation network is coupled to the amplifier output. The compensation network includes at least one RC network tuned to a frequency in which the amplifier operates. The compensation network provides at least one zero to compensate for at least one pole introduced by a load coupled to the amplifier output.
Abstract translation: 放大器包括放大器输入和放大器输出。 补偿网络耦合到放大器输出。 补偿网络包括至少一个调谐到放大器工作频率的RC网络。 补偿网络提供至少一个零以补偿由耦合到放大器输出的负载引入的至少一个极点。
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公开(公告)号:US20150102858A1
公开(公告)日:2015-04-16
申请号:US14508755
申请日:2014-10-07
Applicant: Texas Instruments Incorporated
Inventor: Srinivas K. Pulijala , Steven G. Brantley
CPC classification number: H03F1/02 , H03F1/14 , H03F3/20 , H03F2200/135 , H03F2200/153 , H03F2200/171 , H03F2200/297 , H03F2200/408
Abstract: An amplifier includes an amplifier input and an amplifier output. A compensation network is coupled to the amplifier output. The compensation network includes at least one RC network tuned to a frequency in which the amplifier operates. The compensation network provides at least one zero to compensate for at least one pole introduced by a load coupled to the amplifier output.
Abstract translation: 放大器包括放大器输入和放大器输出。 补偿网络耦合到放大器输出。 补偿网络包括至少一个调谐到放大器工作频率的RC网络。 补偿网络提供至少一个零以补偿由耦合到放大器输出的负载引入的至少一个极点。
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