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公开(公告)号：US20140218091A1
公开(公告)日：2014-08-07
申请号：US13759249
申请日：2013-02-05
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Steven Bartling , Sudhanshu Khanna
IPC: H03K3/012
CPC classification number: H03K3/3562 , G01R31/318541 , H03K3/012 , H03K3/35625
Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.
Abstract translation: 在本发明的实施例中，触发器电路包含2输入多路复用器，主锁存器，传输门和从锁存器。 复用器的扫描使能控制信号SE和SEN确定数据还是扫描数据被输入到主锁存器。 时钟信号CLK和CLKN以及保持控制信号RET和RETN确定主锁存器何时被锁存。 从锁存器被配置为接收主锁存器的输出，第二数据位D2，时钟信号CLK和CLN，保持控制信号RET和RETN，从控制信号SS和SSN。 信号CLK，CLKN，RET，RETN，SS和SSN确定主锁存器或第二数据位D2的输出是否锁存在从锁存器中。 在保持模式期间，控制信号RET和RETN确定数据是否存储在从锁存器中。
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公开(公告)号：US09270257B2
公开(公告)日：2016-02-23
申请号：US14454971
申请日：2014-08-08
Applicant: Texas Instruments Incorporated
Inventor： Steven Bartling , Sudhanshu Khanna
CPC classification number: H03K3/356008
Abstract: In an embodiment of the invention, a dual-port positive level sensitive reset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, reset control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET, the reset control signal REN and the control signals SS and SSN. The signals CKT, CLKZ, RET, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signal RET determines when data is stored in the dual-port latch during retention mode.
Abstract translation: 在本发明的实施例中，双端口正电平敏感复位数据保持锁存器包括时钟反相器和双端口锁存器。 当时钟信号CKT变高，CLKZ变为低电平，复位控制信号REN为高电平，保持控制信号RET为低电平时，数据通过时钟反相器进行时钟控制。 双端口锁存器被配置为接收时钟反相器的输出，第二数据位D2，时钟信号CKT和CLN，保持控制信号RET，复位控制信号REN和控制信号SS和SSN。 信号CKT，CLKZ，RET，REN，SS和SSN确定时钟反相器或第二数据位D2的输出是否锁存在双端口锁存器中。 在保持模式期间，控制信号RET确定数据何时存储在双端口锁存器中。
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公开(公告)号：US09083328B2
公开(公告)日：2015-07-14
申请号：US14457251
申请日：2014-08-12
Applicant: Texas Instruments Incorporated
Inventor： Steven Bartling , Sudhanshu Khanna
IPC: H03K3/289 , H03K3/3562 , G01R31/3185 , H03K3/012
CPC classification number: H03K3/3562 , G01R31/318541 , H03K3/012 , H03K3/35625
Abstract: In an embodiment of the invention, a flip-flop circuit contains a first inverter, a pass gate, master latch, a transfer gate and a slave latch. The clock signals and retention control signals determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals, the retain control signals, the slave control signals. The clock signals, the retain control signals, and the slave control signals determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. The retain control signals determine when data is stored in the slave latch during retention mode.
Abstract translation: 在本发明的实施例中，触发器电路包含第一反相器，通孔，主锁存器，传输门和从锁存器。 时钟信号和保持控制信号确定主锁存器何时被锁存。 从锁存器被配置为接收主锁存器的输出，第二数据位D2，时钟信号，保持控制信号，从控制信号。 时钟信号，保持控制信号和从控制信号确定主锁存器或第二数据位D2的输出是否锁存在从锁存器中。 保留控制信号确定在保持模式期间数据何时存储在从锁存器中。
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公开(公告)号：US09007111B2
公开(公告)日：2015-04-14
申请号：US14154458
申请日：2014-01-14
Applicant: Texas Instruments Incorporated
Inventor： Steven Bartling , Sudhanshu Khanna
IPC: H03K3/356 , H03K3/3562
CPC classification number: H03K3/35625 , H03K3/3562
Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLKN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SS, RE and REN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.
Abstract translation: 在本发明的实施例中，触发器电路包含2输入多路复用器，主锁存器，传输门和从锁存器。 复用器的扫描使能控制信号SE和SEN确定数据还是扫描数据被输入到主锁存器。 时钟信号CKT和CLKZ以及保持控制信号RET和RETN确定主锁存器何时被锁存。 从锁存器被配置为接收主锁存器的输出，第二数据位D2，时钟信号CKT和CLKN，保持控制信号RET和RETN，从控制信号SS和SSN。 信号CKT，CLKZ，RET，RETN，SS，SS，RE和REN确定主锁存器或第二数据位D2的输出是否锁存在从锁存器中。 在保持模式期间，控制信号RET和RETN确定数据是否存储在从锁存器中。
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公开(公告)号：US08836398B2
公开(公告)日：2014-09-16
申请号：US13759240
申请日：2013-02-05
Applicant: Texas Instruments Incorporated
Inventor： Steven Bartling , Sudhanshu Khanna
CPC classification number: H03K3/012 , H03K3/289 , H03K3/35625
Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.
Abstract translation: 在本发明的实施例中，触发器电路包含2输入多路复用器，主锁存器，传输门和从锁存器。 复用器的扫描使能控制信号SE和SEN确定数据还是扫描数据被输入到主锁存器。 时钟信号CLK和CLKN以及保持控制信号RET和RETN确定主锁存器何时被锁存。 从锁存器被配置为接收主锁存器的输出，第二数据位D2，时钟信号CLK和CLN，保持控制信号RET和RETN，从控制信号SS和SSN。 信号CLK，CLKN，RET，RETN，SS和SSN确定主锁存器或第二数据位D2的输出是否锁存在从锁存器中。 在保持模式期间，控制信号RET和RETN确定数据是否存储在从锁存器中。
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Patent Agency Ranking
公开(公告)号：US20140232443A1
公开(公告)日：2014-08-21
申请号：US14154550
申请日：2014-01-14
Applicant: Texas Instruments Incorporated
Inventor： Steven Bartling , Sudhanshu Khanna
IPC: H03K3/3562
CPC classification number: H03K3/35625
Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLKN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.
Abstract translation: 在本发明的实施例中，触发器电路包含2输入多路复用器，主锁存器，传输门和从锁存器。 复用器的扫描使能控制信号SE和SEN确定数据还是扫描数据被输入到主锁存器。 时钟信号CKT和CLKZ以及保持控制信号RET和RETN确定主锁存器何时被锁存。 从锁存器被配置为接收主锁存器的输出，第二数据位D2，时钟信号CKT和CLKN，保持控制信号RET和RETN，从控制信号SS和SSN。 信号CKT，CLKZ，RET，RETN，SS，SSN和PREN确定主锁存器或第二数据位D2的输出是否锁存在从锁存器中。 在保持模式期间，控制信号RET和RETN确定数据是否存储在从锁存器中。
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公开(公告)号：US08803582B1
公开(公告)日：2014-08-12
申请号：US13875438
申请日：2013-05-02
Applicant: Texas Instruments Incorporated
Inventor： Steven Bartling , Sudhanshu Khanna
CPC classification number: H03K3/35625
Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.
Abstract translation: 在本发明的实施例中，触发器电路包含2输入多路复用器，主锁存器，传输门和从锁存器。 复用器的扫描使能控制信号SE和SEN确定数据还是扫描数据被输入到主锁存器。 时钟信号CKT和CLKZ以及保持控制信号RET和RETN确定主锁存器何时被锁存。 从锁存器被配置为接收主锁存器的输出，第二数据位D2，时钟信号CKT和CLN，保持控制信号RET和RETN，从控制信号SS和SSN。 信号CKT，CLKZ，RET，RETN，SS，SSN和PREN确定主锁存器或第二数据位D2的输出是否锁存在从锁存器中。 在保持模式期间，控制信号RET和RETN确定数据是否存储在从锁存器中。
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公开(公告)号：US20140218090A1
公开(公告)日：2014-08-07
申请号：US13759240
申请日：2013-02-05
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Steven Bartling , Sudhanshu Khanna
IPC: H03K3/012
CPC classification number: H03K3/012 , H03K3/289 , H03K3/35625
Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.
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公开(公告)号：US11449341B2
公开(公告)日：2022-09-20
申请号：US16564652
申请日：2019-09-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Marko Krüger , Steven Bartling , Markus Kösler
IPC: G06F9/30 , G06F9/38 , G06F1/3237
Abstract: The invention relates to an electronic device for data processing, which includes an execution unit with a temporary register, a register file, a first feedback path from the data output of the execution unit to the register file, a second feedback path from the data output of the execution unit to the temporary register, a switch configured to connect the first feedback path and/or the second feedback path, and a logic stage coupled to control the switch. The control stage is configured to control the switch to connect the second feedback path if the data output of an execution unit is used as an operand in the subsequent operation of an execution unit.
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公开(公告)号：US09746868B2
公开(公告)日：2017-08-29
申请号：US13768983
申请日：2013-02-15
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Aatmesh Shrivastava , Yogesh Ramadass , Steven Bartling
CPC classification number: G05F3/08 , H02J1/00 , H02M3/1563 , H02M3/1582 , Y10T307/50 , Y10T307/696
Abstract: A system comprising an ambient energy source, a power supply, and a power storage device. The ambient energy source is coupled to a first terminal end of an inductor. The power supply is also coupled to the first terminal end of the inductor. The power storage device is coupled to a second terminal end of the inductor. The ambient energy source provides power through the inductor in a first direction to the power storage device. The power storage device provides power through the inductor to the power supply in a second direction opposite the first direction.
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