公开(公告)号：US20190190521A1

公开(公告)日：2019-06-20

申请号：US16284212

申请日：2019-02-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Venkateswar Reddy Kowkutla ,  Erkan Bilhan ,  Venkateswara Reddy Pothireddy

IPC: H03K19/0175

CPC classification number: H03K19/017509 ,  H03K3/037

Abstract: A method and circuitry that enables an input/output pin (I/O) on a System on a Chip to function either as an analog or as a digital input/output without compromising the overall performance of the system, thus giving the automated test equipment full flexibility to maximize parallel testing for both analog and digital modules.

公开(公告)号：US10256821B2

公开(公告)日：2019-04-09

申请号：US15437593

申请日：2017-02-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Venkateswar Reddy Kowkutla ,  Erkan Bilhan ,  Venkateswara Reddy Pothireddy

IPC: H03K19/017 ,  H03K19/0175 ,  H03K3/037

Abstract: A method and circuitry that enables an input/output pin (I/O) on a System on a Chip to function either as an analog or as a digital input/output without compromising the overall performance of the system, thus giving the automated test equipment full flexibility to maximize parallel testing for both analog and digital modules.

公开(公告)号：US20190058460A1

公开(公告)日：2019-02-21

申请号：US16057211

申请日：2018-08-07

Applicant: Texas Instruments Incorporated

Inventor： Venkateswara Reddy Pothireddy ,  Wahed Abdul Mohammed

IPC: H03K3/012 ,  H03K17/687

Abstract: In a described example, an apparatus includes a driver circuit coupled to an output pad, the driver having a p-channel FET coupled between a positive peripheral voltage and the pad, and having a first gate terminal coupled to a first gate control signal, and an n-channel FET coupled between the pad and a ground terminal and having a second gate terminal coupled to a second gate control signal. A predriver circuit is coupled to receive a data signal for output to the pad and further coupled to output the first gate control signal; and the predriver circuit is coupled to output a supply voltage to the first gate control signal in a first mode, and to output a bias voltage less than the supply voltage to the first gate control signal in a second mode; and a bias circuit is coupled for outputting the bias voltage.