公开(公告)号：US20200209931A1

公开(公告)日：2020-07-02

申请号：US16814625

申请日：2020-03-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Venkateswar Reddy Kowkutla ,  Chunhua Hu ,  Erkan Bilhan ,  Sumant Dinkar Kale

IPC: G06F1/24 ,  G06F1/28

Abstract: A functional safety POR system requires implementing voltage detectors and supervisory functions in a complex SOC. These features are implemented within the SOC without external components. Three stages of voltage monitoring are implemented to ensure redundancy.

公开(公告)号：US10396922B2

公开(公告)日：2019-08-27

申请号：US15891227

申请日：2018-02-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chunhua Hu ,  Venkateswar Reddy Kowkutla ,  Eric Hansen ,  Denis Beaudoin ,  Thomas Anton Leyrer

IPC: H04J3/06 ,  H04L7/00

Abstract: A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

公开(公告)号：US12072731B2

公开(公告)日：2024-08-27

申请号：US18317190

申请日：2023-05-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Varun Singh ,  Rejitha Nair ,  John Chrysostom Apostol ,  Venkateswar Reddy Kowkutla ,  Santhanagopal Raghavendra

IPC: G06F1/12 ,  G06F1/08 ,  G06F1/10 ,  H03K21/08 ,  H03K19/20

CPC classification number: G06F1/12 ,  G06F1/08 ,  G06F1/10 ,  H03K21/08 ,  H03K19/20

Abstract: An electronic device comprising one or more subcircuits configured to receive a clock signal, the clock signal configured to switch from a reference clock signal to a second clock signal based on a clock bypass signal, a timer configured to receive the reference clock signal and output an alignment signal based on the reference clock signal, wherein a frequency of the alignment signal is determined based on clock frequencies of the one or more subcircuits; a clock alignment module coupled to the timer and the one or more subcircuits and configured to receive the clock bypass signal, determine that the clock bypass signal has changed to switch the one or more subcircuits to the reference clock signal from the second clock signal, block the clock signal from being received by the one or more subcircuits, receive the alignment signal, and unblock the clock signal based on the alignment signal.

公开(公告)号：US11662763B1

公开(公告)日：2023-05-30

申请号：US17537150

申请日：2021-11-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Varun Singh ,  Rejitha Nair ,  John Chrysostom Apostol ,  Venkateswar Reddy Kowkutla ,  Raghavendra Santhanagopal

IPC: G06F1/12 ,  H03K21/08 ,  G06F1/08 ,  G06F1/10 ,  H03K19/20

CPC classification number: G06F1/12 ,  G06F1/08 ,  G06F1/10 ,  H03K21/08 ,  H03K19/20

Abstract: An electronic device comprising one or more subcircuits configured to receive a clock signal, the clock signal configured to switch from a reference clock signal to a second clock signal based on a clock bypass signal, a timer configured to receive the reference clock signal and output an alignment signal based on the reference clock signal, wherein a frequency of the alignment signal is determined based on clock frequencies of the one or more subcircuits; a clock alignment module coupled to the timer and the one or more subcircuits and configured to receive the clock bypass signal, determine that the clock bypass signal has changed to switch the one or more subcircuits to the reference clock signal from the second clock signal, block the clock signal from being received by the one or more subcircuits, receive the alignment signal, and unblock the clock signal based on the alignment signal.

公开(公告)号：US11509302B2

公开(公告)日：2022-11-22

申请号：US17080239

申请日：2020-10-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chunhua Hu ,  Venkateswar Reddy Kowkutla ,  Charles Fuoco

IPC: H03K17/22

Abstract: Disclosed embodiments include an electronic system with a power on reset (POR) circuit. The POR circuit includes first voltage detection circuitry to perform a first detection on a supply voltage and to output a first control signal in response to the first detection, second voltage detection circuitry to perform a second detection on the supply voltage and to output a second control signal in response to the second detection, and third voltage detection circuitry to perform a third detection on the supply voltage and to output at least one third control signal in response to the third detection. The POR circuit further has sequencing circuitry with a first input to receive the at least one third control signal and to output a reset signal in response to the at least one third control signal.

公开(公告)号：US11269389B2

公开(公告)日：2022-03-08

申请号：US16814625

申请日：2020-03-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Venkateswar Reddy Kowkutla ,  Chunhua Hu ,  Erkan Bilhan ,  Sumant Dinkar Kale

IPC: G06F1/24 ,  G06F1/28

Abstract: A functional safety POR system requires implementing voltage detectors and supervisory functions in a complex SOC. These features are implemented within the SOC without external components. Three stages of voltage monitoring are implemented to ensure redundancy.

公开(公告)号：US10574235B2

公开(公告)日：2020-02-25

申请号：US16284212

申请日：2019-02-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Venkateswar Reddy Kowkutla ,  Erkan Bilhan ,  Venkateswara Reddy Pothireddy

IPC: H03K19/0175 ,  H03K3/037

Abstract: A method and circuitry that enables an input/output pin (I/O) on a System on a Chip to function either as an analog or as a digital input/output without compromising the overall performance of the system, thus giving the automated test equipment full flexibility to maximize parallel testing for both analog and digital modules.

公开(公告)号：US20180189156A1

公开(公告)日：2018-07-05

申请号：US15395156

申请日：2016-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chunhua Hu ,  Venkateswar Reddy Kowkutla ,  Charles Fuoco

IPC: G06F11/22 ,  G06F1/28

CPC classification number: G06F1/24 ,  G06F1/28 ,  G06F11/22

Abstract: The reset isolation mechanism describes an embedded safety island inside a system on a chip which reduces the overall system cost while achieving functional safety. The safety island ensures an orderly shutdown of all or part of the rest of the system on a chip without the possibility of a safety island hang due to incomplete transactions at the time of the reset.

公开(公告)号：US11196424B2

公开(公告)日：2021-12-07

申请号：US17078708

申请日：2020-10-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jose Luis Flores ,  Venkateswar Reddy Kowkutla ,  Ramakrishnan Venkatasubramanian

IPC: H03L7/08 ,  H03K19/20 ,  G06F1/10 ,  G06F1/08 ,  H03K5/00

Abstract: An integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to divider output, the second clock input coupled to the reference clock input, and the bypass logic output coupled to the clock domain input. The bypass logic selectively bypasses the PLL and divider responsive to a bypass control signal triggered by a reset signal. The reset signal also triggers a reset control signal delayed relative to the bypass control signal.

公开(公告)号：US10819334B2

公开(公告)日：2020-10-27

申请号：US16299544

申请日：2019-03-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chunhua Hu ,  Venkateswar Reddy Kowkutla ,  Charles Fuoco

IPC: H03K17/22

Abstract: Disclosed embodiments include an electronic system with a power on reset (POR) circuit. The POR circuit includes first voltage detection circuitry to perform a first detection on a supply voltage and to output a first control signal in response to the first detection, second voltage detection circuitry to perform a second detection on the supply voltage and to output a second control signal in response to the second detection, and third voltage detection circuitry to perform a third detection on the supply voltage and to output at least one third control signal in response to the third detection. The POR circuit further has sequencing circuitry with a first input to receive the at least one third control signal and to output a reset signal in response to the at least one third control signal.