公开(公告)号：US20170141101A1

公开(公告)日：2017-05-18

申请号：US15368958

申请日：2016-12-05

Applicant: Texas Instruments Incorporated

Inventor： Weidong Tian ,  YuGuo Wang ,  Tathagata Chatterjee ,  Rajni J. Aggarwal

IPC: H01L27/06 ,  H01L29/06 ,  H01L21/8249 ,  H01L29/45 ,  H01L29/417 ,  H01L29/739 ,  H01L29/10

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L27/092 ,  H01L29/0688 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/423 ,  H01L29/456 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7395

Abstract: An integrated circuit includes an NMOS transistor, a PMOS transistor and a vertical bipolar transistor. The vertical bipolar transistor has an intrinsic base with a band barrier at least 25 meV high at a surface boundary of the intrinsic base, except at an emitter-base junction with an emitter, and except at a base-collector junction with a collector. The intrinsic base may be laterally surrounded by an extrinsic base with a higher dopant density than the intrinsic base, wherein a higher dopant density provides the band barrier at lateral surfaces of the intrinsic base. A gate may be disposed on a gate dielectric layer over a top surface boundary of the intrinsic base adjacent to the emitter. The gate is configured to accumulate the intrinsic base immediately under the gate dielectric layer, providing the band barrier at the top surface boundary of the intrinsic base.

公开(公告)号：US09431253B1

公开(公告)日：2016-08-30

申请号：US14819401

申请日：2015-08-05

Applicant: Texas Instruments Incorporated

Inventor： Ning Tan ,  Weidong Tian

IPC: H01L21/336 ,  H01L21/3205 ,  H01L21/266 ,  H01L27/115 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/265 ,  H01L27/105

CPC classification number: H01L27/11521 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28008 ,  H01L21/28273 ,  H01L21/761 ,  H01L21/823412 ,  H01L21/823443 ,  H01L21/823456 ,  H01L21/823814 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543 ,  H01L29/0847 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/45 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66825

Abstract: An integrated circuit contains a flash cell in which the top gate of the sense transistor is a metal sense gate over the floating gate. The source/drain regions of the sense transistor extend under the floating gate so that the source region is separated from the drain region by a sense channel length less than 200 nanometers. The floating gate is at least 400 nanometers wide, so the source/drain regions of the sense transistor extend under the floating gate at least 100 nanometers on each side. The integrated circuit is formed by forming the sense transistor source and drain regions before forming the floating gate.

Abstract translation: 集成电路包含闪存单元，其中感测晶体管的顶栅极是浮置栅极上的金属感测栅极。 感测晶体管的源极/漏极区域在浮置栅极下方延伸，使得源极区域与漏极区域分离，其感测沟道长度小于200纳米。 浮置栅极至少为400纳米宽，因此感测晶体管的源极/漏极区域在浮置栅极下方每侧至少延伸100纳米。 集成电路通过在形成浮置栅极之前形成感测晶体管源极和漏极区域而形成。

公开(公告)号：US10109574B1

公开(公告)日：2018-10-23

申请号：US15478615

申请日：2017-04-04

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. West ,  Byron Lovell Williams ,  David Leonard Larkin ,  Weidong Tian

IPC: H01L23/48 ,  H01L23/52 ,  H01L21/02 ,  H01L49/02 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A method and structure for improving high voltage breakdown reliability of a microelectronic device, e.g., a galvanic digital isolator, involves providing an abatement structure around metal plate corners of a high voltage isolation capacitor to ameliorate the effects of an electric field formed thereat during operation of the device due to dielectric discontinuity.

公开(公告)号：US08546222B1

公开(公告)日：2013-10-01

申请号：US13899369

申请日：2013-05-21

Applicant: Texas Instruments Incorporated

Inventor： Shanjen Pan ,  Allan T. Mitchell ,  Weidong Tian

IPC: H01L21/336

CPC classification number: H01L27/0733 ,  H01L21/82 ,  H01L23/525 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In an embodiment of the invention, a method of fabricating a floating-gate PMOSFET (p-type metal-oxide semiconductor field-effect transistor) is disclosed. A silicide blocking layer (e.g. oxide, nitride) is used not only to block areas from being silicided but to also form an insulator on top of a poly-silicon gate. The insulator along with a top electrode (control gate) forms a capacitor on top of the poly-silicon gate. The poly-silicon gate also serves at the bottom electrode of the capacitor. The capacitor can then be used to capacitively couple charge to the poly-silicon gate. Because the poly-silicon gate is surrounded by insulating material, the charge coupled to the poly-silicon gate may be stored for a long period of time after a programming operation.

Abstract translation: 在本发明的实施例中，公开了制造浮栅PMOSFET（p型金属氧化物半导体场效应晶体管）的方法。 硅化物阻挡层（例如氧化物，氮化物）不仅用于阻挡不被硅化的区域，而且还在多晶硅栅极的顶部形成绝缘体。 绝缘体与顶部电极（控制栅极）一起形成在多晶硅栅极顶部的电容器。 多晶硅栅极还用于电容器的底部电极。 然后可以使用电容器将电荷电容耦合到多晶硅栅极。 由于多晶硅栅极被绝缘材料包围，所以耦合到多晶硅栅极的电荷可以在编程操作之后长时间存储。