公开(公告)号：US12009256B2

公开(公告)日：2024-06-11

申请号：US18338095

申请日：2023-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Wen-Hsiung Lu ,  Chin Wei Kang ,  Yung-Han Chuang ,  Lung-Kai Mao ,  Yung-Sheng Lin

IPC: H01L21/768 ,  H01L23/00

CPC classification number: H01L21/76885 ,  H01L21/76802 ,  H01L21/76852 ,  H01L21/76871 ,  H01L24/05 ,  H01L24/13 ,  H01L24/32 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022

Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

公开(公告)号：US20230352342A1

公开(公告)日：2023-11-02

申请号：US18338095

申请日：2023-06-20

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Ming-Da Cheng ,  Wen-Hsiung Lu ,  Chin Wei Kang ,  Yung-Han Chuang ,  Lung-Kai Mao ,  Yung-Sheng Lin

IPC: H01L21/768 ,  H01L23/00

CPC classification number: H01L21/76885 ,  H01L21/76802 ,  H01L21/76852 ,  H01L21/76871 ,  H01L24/05 ,  H01L24/13 ,  H01L24/32 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022

Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

公开(公告)号：US20220336275A1

公开(公告)日：2022-10-20

申请号：US17809957

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Ming-Da Cheng ,  Wen-Hsiung Lu ,  Chin Wei Kang ,  Yung-Han Chuang ,  Lung-Kai Mao ,  Yung-Sheng Lin

IPC: H01L21/768 ,  H01L23/00

Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

公开(公告)号：US11387143B2

公开(公告)日：2022-07-12

申请号：US17085619

申请日：2020-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Wen-Hsiung Lu ,  Chin Wei Kang ,  Yung-Han Chuang ,  Lung-Kai Mao ,  Yung-Sheng Lin

IPC: H01L21/768 ,  H01L23/00

Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.