公开(公告)号：US20230411318A1

公开(公告)日：2023-12-21

申请号：US18231032

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Po-Hao Tsai ,  Ming-Da Cheng ,  Yung-Han Chuang ,  Hsueh-Sheng Wang

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L24/14 ,  H01L24/11 ,  H01L2924/3841 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/06051 ,  H01L2224/0231 ,  H01L2224/03462 ,  H01L2224/11849 ,  H01L2224/0603 ,  H01L2224/02331 ,  H01L2224/05017 ,  H01L2224/1403 ,  H01L2224/14051

Abstract: Methods for forming under-bump metallurgy (UBM) structures having different surface profiles and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a first under-bump metallurgy (UBM) structure over and electrically coupled to the first redistribution line, the first UBM structure extending through the first passivation layer, a top surface of the first UBM structure being concave; and a second UBM structure over and electrically coupled to the second redistribution line, the second UBM structure extending through the first passivation layer, a top surface of the second UBM structure being flat or convex.

公开(公告)号：US11855017B2

公开(公告)日：2023-12-26

申请号：US17342869

申请日：2021-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Po-Hao Tsai ,  Ming-Da Cheng ,  Yung-Han Chuang ,  Hsueh-Sheng Wang

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/03462 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/11849 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2924/3841

Abstract: Methods for forming under-bump metallurgy (UBM) structures having different surface profiles and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a first under-bump metallurgy (UBM) structure over and electrically coupled to the first redistribution line, the first UBM structure extending through the first passivation layer, a top surface of the first UBM structure being concave; and a second UBM structure over and electrically coupled to the second redistribution line, the second UBM structure extending through the first passivation layer, a top surface of the second UBM structure being flat or convex.

公开(公告)号：US12243837B2

公开(公告)日：2025-03-04

申请号：US18231032

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Po-Hao Tsai ,  Ming-Da Cheng ,  Yung-Han Chuang ,  Hsueh-Sheng Wang

IPC: H01L23/00

Abstract: Methods for forming under-bump metallurgy (UBM) structures having different surface profiles and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a first under-bump metallurgy (UBM) structure over and electrically coupled to the first redistribution line, the first UBM structure extending through the first passivation layer, a top surface of the first UBM structure being concave; and a second UBM structure over and electrically coupled to the second redistribution line, the second UBM structure extending through the first passivation layer, a top surface of the second UBM structure being flat or convex.

公开(公告)号：US20240290656A1

公开(公告)日：2024-08-29

申请号：US18655989

申请日：2024-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Wen-Hsiung Lu ,  Chin Wei Kang ,  Yung-Han Chuang ,  Lung-Kai Mao ,  Yung-Sheng Lin

IPC: H01L21/768 ,  H01L23/00

CPC classification number: H01L21/76885 ,  H01L21/76802 ,  H01L21/76852 ,  H01L21/76871 ,  H01L24/05 ,  H01L24/13 ,  H01L24/32 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022

Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

公开(公告)号：US20240250019A1

公开(公告)日：2024-07-25

申请号：US18598266

申请日：2024-03-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Po-Hao Tsai ,  Ming-Da Cheng ,  Yung-Han Chuang ,  Hsueh-Sheng Wang

IPC: H01L23/522 ,  H01L21/48 ,  H01L23/00 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/486 ,  H01L23/528 ,  H01L24/11 ,  H01L24/14

Abstract: Methods for forming dummy under-bump metallurgy structures and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a second passivation layer over the first passivation layer; a first under-bump metallurgy (UBM) structure over the first redistribution line, the first UBM structure extending through the first passivation layer and the second passivation layer and being electrically coupled to the first redistribution line; and a second UBM structure over the second redistribution line, the second UBM structure extending through the second passivation layer, the second UBM structure being electrically isolated from the second redistribution line by the first passivation layer.

公开(公告)号：US11721579B2

公开(公告)日：2023-08-08

申请号：US17809957

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Wen-Hsiung Lu ,  Chin Wei Kang ,  Yung-Han Chuang ,  Lung-Kai Mao ,  Yung-Sheng Lin

IPC: H01L21/768 ,  H01L23/00

CPC classification number: H01L21/76885 ,  H01L21/76802 ,  H01L21/76852 ,  H01L21/76871 ,  H01L24/05 ,  H01L24/13 ,  H01L24/32 ,  H01L2224/0231 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/02331 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022

Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

公开(公告)号：US20220223548A1

公开(公告)日：2022-07-14

申请号：US17342869

申请日：2021-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Po-Hao Tsai ,  Ming-Da Cheng ,  Yung-Han Chuang ,  Hsueh-Sheng Wang

IPC: H01L23/00

Abstract: Methods for forming under-bump metallurgy (UBM) structures having different surface profiles and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a first under-bump metallurgy (UBM) structure over and electrically coupled to the first redistribution line, the first UBM structure extending through the first passivation layer, a top surface of the first UBM structure being concave; and a second UBM structure over and electrically coupled to the second redistribution line, the second UBM structure extending through the first passivation layer, a top surface of the second UBM structure being flat or convex.

公开(公告)号：US20210375674A1

公开(公告)日：2021-12-02

申请号：US17085619

申请日：2020-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Wen-Hsiung Lu ,  Chin Wei Kang ,  Yung-Han Chuang ,  Lung-Kai Mao ,  Yung-Sheng Lin

IPC: H01L21/768 ,  H01L23/00

Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

公开(公告)号：US12009256B2

公开(公告)日：2024-06-11

申请号：US18338095

申请日：2023-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Wen-Hsiung Lu ,  Chin Wei Kang ,  Yung-Han Chuang ,  Lung-Kai Mao ,  Yung-Sheng Lin

IPC: H01L21/768 ,  H01L23/00

CPC classification number: H01L21/76885 ,  H01L21/76802 ,  H01L21/76852 ,  H01L21/76871 ,  H01L24/05 ,  H01L24/13 ,  H01L24/32 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022

Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

公开(公告)号：US11955423B2

公开(公告)日：2024-04-09

申请号：US17213650

申请日：2021-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Po-Hao Tsai ,  Ming-Da Cheng ,  Yung-Han Chuang ,  Hsueh-Sheng Wang

IPC: H01L21/768 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/495 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065

CPC classification number: H01L23/5226 ,  H01L21/486 ,  H01L23/528 ,  H01L24/11 ,  H01L24/14

Abstract: Methods for forming dummy under-bump metallurgy structures and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a second passivation layer over the first passivation layer; a first under-bump metallurgy (UBM) structure over the first redistribution line, the first UBM structure extending through the first passivation layer and the second passivation layer and being electrically coupled to the first redistribution line; and a second UBM structure over the second redistribution line, the second UBM structure extending through the second passivation layer, the second UBM structure being electrically isolated from the second redistribution line by the first passivation layer.