公开(公告)号：US20210376124A1

公开(公告)日：2021-12-02

申请号：US17395195

申请日：2021-08-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Tsai ,  Fu-Yao Nien ,  Hong-Wei Huang ,  Chang-Sheng Lee

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065

Abstract: A semiconductor device includes a substrate, an isolation structure on the substrate, a fin protruding from the substrate and through the isolation structure, a gate stack engaging the fin, and a gate spacer on sidewalls of the gate stack. The gate spacer includes an inner sidewall facing the gate stack and an outer sidewall opposing the inner sidewall. The inner sidewall has a first height measured from a top surface of the fin and a bowed structure in a top portion of the inner sidewall. The bowed structure extends towards the gate stack for a first lateral distance measured from a middle point of the inner sidewall. The first lateral distance is less than about 8% of the first height.

公开(公告)号：US11088262B2

公开(公告)日：2021-08-10

申请号：US16573552

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Tsai ,  Fu-Yao Nien ,  Hong-Wei Huang ,  Chang-Sheng Lee

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065

Abstract: A method includes providing a structure having a substrate and a fin protruding from the substrate; forming a dummy gate stack over the fin; forming a gate spacer on sidewalls of the dummy gate stack; removing the dummy gate stack using a radical etch process, resulting in a gate trench; and forming a metal gate stack in the gate trench.

公开(公告)号：US10166650B2

公开(公告)日：2019-01-01

申请号：US15221187

申请日：2016-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Liang Cheng ,  Yen-Yu Chen ,  Chang-Sheng Lee ,  Wei Zhang

IPC: B24B37/00 ,  B24B37/013 ,  H01L21/66 ,  H01L21/67 ,  H01L21/306 ,  H01L21/3105 ,  B24B49/12 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

Abstract: A chemical-mechanical planarization (CMP) system includes a platen, a pad, a polish head, a rotating mechanism, a light source, and a detector. The pad is disposed on the platen. The polish head is configured to hold a wafer against the pad. The rotating mechanism is configured to rotate at least one of the platen and the polish head. The light source is configured to provide incident light to an end-point layer on the wafer. The detector is configured to detect absorption of the incident light by the end-point layer.

公开(公告)号：US09553160B2

公开(公告)日：2017-01-24

申请号：US14049657

申请日：2013-10-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Jen Chen ,  Yen-Yu Chen ,  Chang-Sheng Lee ,  Wei Zhang

IPC: H01L21/66 ,  G01R31/26 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L29/4966 ,  H01L21/28194 ,  H01L22/12 ,  H01L22/20 ,  H01L29/513 ,  H01L29/517

Abstract: Embodiments of mechanisms of monitoring metal impurity in a high-k dielectric film are provided. The method includes forming an interfacial layer over a substrate. The method also includes forming a high-k dielectric film on the interfacial layer, and the interfacial layer and the high-k dielectric film form a stacked structure over the substrate. The method further includes conducting the first thickness measurement on the stacked structure. In addition, the method includes performing a treatment to the stacked structure after the first thickness measurement, and the treatment includes an annealing process. The method also includes conducting the second thickness measurement on the stacked structure after the treatment.

Abstract translation: 提供了在高k电介质膜中监测金属杂质的机理的实施例。 该方法包括在衬底上形成界面层。 该方法还包括在界面层上形成高k电介质膜，并且界面层和高k电介质膜在衬底上形成堆叠结构。 该方法还包括对堆叠结构进行第一厚度测量。 此外，该方法包括在第一厚度测量之后对堆叠结构进行处理，并且处理包括退火处理。 该方法还包括在处理之后对堆叠结构进行第二厚度测量。