公开(公告)号：US20230238443A1

公开(公告)日：2023-07-27

申请号：US18129961

申请日：2023-04-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ming LIN ,  Sai-Hooi YEONG ,  Ziwei FANG ,  Chi On CHUI ,  Huang-Lin CHAO

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/516 ,  H01L29/7851 ,  H01L21/02356 ,  H01L21/28176 ,  H01L29/66795 ,  H01L27/0886 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/785

Abstract: The present disclosure describes a device that is protected from the effects of an oxide on the metal gate layers of ferroelectric field effect transistors. In some embodiments, the device includes a substrate with fins thereon; an interfacial layer on the fins; a crystallized ferroelectric layer on the interfacial layer; and a metal gate layer on the ferroelectric layer,

公开(公告)号：US20210328064A1

公开(公告)日：2021-10-21

申请号：US17328145

申请日：2021-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming LIN ,  Sai-Hooi Yeong ,  Ziwei Fang ,  Chi On Chui ,  Huang-Lin Chao

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02

Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.

公开(公告)号：US20210083068A1

公开(公告)日：2021-03-18

申请号：US16573498

申请日：2019-09-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ming LIN ,  Sai-Hooi YEONG ,  Ziwei FANG ,  Chi On CHUI ,  Huang-Lin CHAO

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02

Abstract: The present disclosure describes a method that can eliminate or minimize the formation of an oxide on the metal gate layers of ferroelectric field effect transistors. In some embodiments, the method includes providing a substrate with fins thereon; depositing an interfacial layer on the fins; depositing a ferroelectric layer on the interfacial layer; depositing a metal gate layer on the ferroelectric layer; exposing the metal gate layer to a metal-halide gas; and performing a post metallization annealing, where the exposing the metal gate layer to the metal-halide gas and the performing the post metallization annealing occur without a vacuum break.

公开(公告)号：US20240395882A1

公开(公告)日：2024-11-28

申请号：US18789360

申请日：2024-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ming LIN ,  Peng-Soon LIM ,  Zi-Wei FANG

IPC: H01L29/417 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes following steps. A semiconductor fin is formed extending from a substrate. A gate dielectric layer is formed to wrap around semiconductor fin. A P-type work function layer is formed to wrap around the gate dielectric layer. An N-type work function layer is formed to wrap around the P-type work function layer. The N-type work function layer has a work function different from a work function of the P-type work function layer. The N-type work function layer is treated such that an upper portion of the N-type work function layer has a different composition than a lower portion of the N-type work function layer.

公开(公告)号：US20230207695A1

公开(公告)日：2023-06-29

申请号：US18175346

申请日：2023-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming LIN ,  Sai-Hooi YEONG ,  Ziwei FANG ,  Chi On CHUI ,  Huang-Lin CHAO

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L29/78391 ,  H01L21/02068 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/7851 ,  H01L29/40111 ,  H01L29/66795

Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.

公开(公告)号：US20220310800A1

公开(公告)日：2022-09-29

申请号：US17533575

申请日：2021-11-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal Abhijith Khaderbad ,  Wei-Yen WOON ,  Cheng-Ming LIN ,  Han-Yu LIN ,  Szu-Hua CHEN

IPC: H01L29/40 ,  H01L29/417 ,  H01L21/285

Abstract: The present disclosure describes a semiconductor device and a method for forming the semiconductor device. The method includes forming a fin structure on a substrate, forming a gate structure on the fin structure, and forming a source/drain (S/D) region on the fin structure not covered by the gate structure. The method further includes forming a contact structure on the S/D region. Forming the contact structure includes forming a transition metal chalcogenide (TMC) layer on the S/D region, and forming a contact plug on the TMC layer.

公开(公告)号：US20210328065A1

公开(公告)日：2021-10-21

申请号：US17362317

申请日：2021-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming LIN ,  Sai-Hooi YEONG ,  Ziwei FANG ,  Bo-Feng YOUNG ,  Chi On CHUI ,  Chih-Yu CHANG ,  Huang-Lin CHAO

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L29/66 ,  H01L21/28

Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.

公开(公告)号：US20210083120A1

公开(公告)日：2021-03-18

申请号：US16572255

申请日：2019-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming LIN ,  Sai-Hooi YEONG ,  Ziwei FANG ,  Chi On CHUI ,  Huang-Lin CHAO

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/66

Abstract: The present disclosure relates to methods for forming a semiconductor device. The method includes forming a substrate and forming first and second spacers on the substrate. The method includes depositing first and second self-assembly (SAM) layers respectively on sidewalls of the first and second spacers and depositing a layer stack on the substrate and between and in contact with the first and second SAM layers. Depositing the layer stack includes depositing a ferroelectric layer and removing the first and second SAM layers. The method further includes depositing a metal compound layer on the ferroelectric layer. Portions of the metal compound layer are deposited between the ferroelectric layer and the first or second spacers. The method also includes depositing a gate electrode on the metal compound layer and between the first and second spacers.

公开(公告)号：US20200371425A1

公开(公告)日：2020-11-26

申请号：US16989744

申请日：2020-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh TIEN ,  Cheng-Hsuen CHIANG ,  Chih-Ming CHEN ,  Cheng-Ming LIN ,  Yen-Wei HUANG ,  Hao-Ming CHANG ,  Kuo-Chin LIN ,  Kuan-Shien LEE

IPC: G03F1/32 ,  G03F1/38

Abstract: In a method of manufacturing a photo mask, a resist layer is formed over a mask blank, which includes a mask substrate, a phase shift layer disposed on the mask substrate and a light blocking layer disposed on the phase shift layer. A resist pattern is formed by using a lithographic operation. The light blocking layer is patterned by using the resist pattern as an etching mask. The phase shift layer is patterned by using the patterned light blocking layer as an etching mask. A border region of the mask substrate is covered with an etching hard cover, while a pattern region of the mask substrate is opened. The patterned light blocking layer in the pattern region is patterned through the opening of the etching hard cover. A photo-etching operation is performed on the pattern region to remove residues of the light blocking layer.