公开(公告)号：US20220199403A1

公开(公告)日：2022-06-23

申请号：US17646103

申请日：2021-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Christine Y. OUYANG ,  Ziwei FANG

IPC: H01L21/02 ,  C23C16/02 ,  C23C16/455 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/285

Abstract: The present disclosure relates to a method of fabricating a semiconductor structure, the method includes forming an opening and depositing a metal layer in the opening. The depositing includes performing one or more deposition cycles, wherein each deposition cycle includes flowing a first precursor into a deposition chamber and performing an ultraviolet (UV) radiation process on the first precursor. The method further includes performing a first purging process in the deposition chamber to remove at least a portion of the first precursor, flowing a second precursor into the deposition chamber, and purging the deposition chamber to remove at least a portion of the second precursor.

公开(公告)号：US20210366785A1

公开(公告)日：2021-11-25

申请号：US17397186

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Ziwei FANG

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/423 ,  H01L27/092 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3213 ,  H01L29/49

Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes first and second nanostructured channel regions in first and second nanostructured layers, respectively, and first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The first GAA structure includes an Al-based gate stack with a first gate dielectric layer, an Al-based n-type work function metal layer, a first metal capping layer, and a first gate metal fill layer. The second GAA structure includes an Al-free gate stack with a second gate dielectric layer, an Al-free p-type work function metal layer, a metal growth inhibition layer, a second metal capping layer, and a second gate metal fill layer.

公开(公告)号：US20210020786A1

公开(公告)日：2021-01-21

申请号：US16515898

申请日：2019-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming LIN ,  Sai-Hooi YEONG ,  Ziwei FANG ,  Bo-Feng YOUNG ,  Chi On CHUI ,  Chih-Yu CHANG ,  Huang-Lin CHAO

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer,

公开(公告)号：US20170352574A1

公开(公告)日：2017-12-07

申请号：US15171806

申请日：2016-06-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kei-Wei CHEN ,  Chun-Hsiung TSAI ,  Huai-Tei YANG ,  Shiu-Ko JANGJIAN ,  Ying-Lang WANG ,  Ziwei FANG

IPC: H01L21/687 ,  H01L21/3065 ,  H01J37/32 ,  H01L21/67

CPC classification number: H01L21/68764 ,  H01J37/32082 ,  H01J37/32422 ,  H01J37/3244 ,  H01L21/3065

Abstract: An apparatus for treating a wafer is provided. The apparatus includes a platen, a chamber, an etch gas supplier and a tilting mechanism. The chamber has at least one aperture at least partially facing to the platen. The etch gas supplier is fluidly connected to the chamber. The tilting mechanism is coupled with the platen for allowing the platen to have at least one first degree of freedom to tilt relative to the aperture of the chamber.

公开(公告)号：US20210249308A1

公开(公告)日：2021-08-12

申请号：US17301482

申请日：2021-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  I-Ming CHANG ,  Hsiang-Pi CHANG ,  Yu-Wei LU ,  Ziwei FANG ,  Huang-Lin CHAO

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L21/02

Abstract: An integrated circuit device is provided that includes a first fin structure and a second fin structure extending from a substrate. The first fin structure is a first composition, and includes rounded corners. The second fin structure is a second composition, different than the first composition. A first interface layer is formed directly on the first fin structure including the rounded corners and a second interface layer directly on the second fin structure. The first interface layer is an oxide of the first composition and the second interface layer is an oxide of the second composition. A gate dielectric layer is formed over the first interface layer and the second interface layer.

公开(公告)号：US20200303260A1

公开(公告)日：2020-09-24

申请号：US16897234

申请日：2020-06-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yasutoshi OKUNO ,  Cheng-Yi PENG ,  Ziwei FANG ,  I-Ming CHANG ,  Akira MINEJI ,  Yu-Ming LIN ,  Meng-Hsuan HSIAO

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/203 ,  H01L27/092 ,  H01L21/8238

Abstract: A method of forming a semiconductor device including a fin field effect transistor (FinFET) includes forming a first sacrificial layer over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of the opening and on at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, forming a dielectric layer in the opening. After the dielectric layer is formed, removing the patterned first sacrificial layer, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening. The FinFET is an n-type FET, and the source/drain structure includes an epitaxial layer including Si1−x−yM1xM2y, where M1 includes Sn, M2 is one or more of P and As, and 0.01≤x≤0.1, and 0.01≤y≤0.1.

公开(公告)号：US20200273700A1

公开(公告)日：2020-08-27

申请号：US16281723

申请日：2019-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Ziwei FANG

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/51 ,  H01L29/40

Abstract: A method of fabricating semiconductor devices is provided. The method includes forming an interfacial layer on a substrate, and depositing a gate dielectric layer on the interfacial layer. The method also includes treating the gate dielectric layer with a first post deposition annealing (PDA) process. The method further includes depositing a first capping layer on the gate dielectric layer, and treating the gate dielectric layer by performing a post metal annealing (PMA) process on the first capping layer. In addition, the method includes removing the first capping layer, and treating the gate dielectric layer with a second PDA process. The method also includes forming a gate electrode layer on the gate dielectric layer.

公开(公告)号：US20200152513A1

公开(公告)日：2020-05-14

申请号：US16745769

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Ziwei FANG

IPC: H01L21/768 ,  H01L21/311

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first conductive feature over a semiconductor substrate. The method includes forming an oxygen-absorbing layer on a surface of the first conductive feature. The oxygen-absorbing layer absorbs oxygen from the first conductive feature and becomes an oxygen-containing layer. The method includes removing the oxygen-containing layer to expose the surface originally covered by the oxygen-containing layer. The method includes forming a metal-containing layer on the surface. The method includes forming a second conductive feature on the metal-containing layer.

公开(公告)号：US20190229012A1

公开(公告)日：2019-07-25

申请号：US16371847

申请日：2019-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsan-Chun WANG ,  De-Wei YU ,  Ziwei FANG ,  Yi-Fan CHEN

IPC: H01L21/768 ,  H01L21/265 ,  H01L23/522 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/324 ,  H01L23/48

CPC classification number: H01L21/76825 ,  H01L21/02321 ,  H01L21/02337 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76828 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/5226 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A method of forming a semiconductor device includes depositing a flowable dielectric layer on a substrate and annealing the flowable dielectric layer. The method further includes performing a high temperature (HT) doping process on the flowable dielectric layer. The HT doping process may include implanting dopant ions into the flowable dielectric layer and heating the substrate during the implanting of the dopant ions. The heating of the substrate may include heating a substrate holder upon which the substrate is disposed and maintaining the substrate at a temperature above 100° C. An example benefit reduced the wet etch rate (WER) of the flowable dielectric layer.

公开(公告)号：US20180096898A1

公开(公告)日：2018-04-05

申请号：US15282981

申请日：2016-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： De-Wei YU ,  Chia-Ping LO ,  Liang-Gi YAO ,  Weng CHANG ,  Yee-Chia YEO ,  Ziwei FANG

IPC: H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/823821 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/268 ,  H01L21/324 ,  H01L21/3247 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of semiconductor device fabrication includes providing a substrate including a first fin element and a second fin element extending from the substrate. A first layer is formed over the first and second fin elements, where the first layer includes a gap. A laser anneal process is performed to the substrate to remove the gap in the first layer. An energy applied to the first layer during the laser anneal process is adjusted based on a height of the first layer.