公开(公告)号：US20140264440A1

公开(公告)日：2014-09-18

申请号：US14182777

申请日：2014-02-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsuing Chen ,  Ling-Sung Wang ,  Chi-Yen Lin

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/30604 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/7848

Abstract: Some embodiments of the present disclosure relates to a method and a device to achieve a strained channel. A volume of a source or drain recess is controlled by a performing an etch of a substrate to produce a recess. An anisotropic etch stop layer is then formed by doping a bottom surface of the recess with a boron-containing dopant, which distorts the crystalline structure of the bottom surface. An anisotropic etch of the recess is then performed. The anisotropic etch stop layer resists anisotropic etching such that the recess comprises a substantially flat bottom surface after the anisotropic etch. The source or drain recess is then filled with a stress-inducing material to produce a strained channel.

Abstract translation: 本公开的一些实施例涉及实现应变信道的方法和装置。 通过对衬底进行蚀刻来产生凹陷来控制源极或漏极凹槽的体积。 然后通过用含硼掺杂剂掺杂凹陷的底表面来形成各向异性蚀刻停止层，这使得底表面的晶体结构变形。 然后进行凹陷的各向异性蚀刻。 各向异性蚀刻停止层抵抗各向异性蚀刻，使得凹陷在各向异性蚀刻之后包括基本平坦的底表面。 然后用引发应力的材料填充源极或漏极凹槽以产生应变通道。

公开(公告)号：US12052851B2

公开(公告)日：2024-07-30

申请号：US17885166

申请日：2022-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Gulbagh Singh ,  Shun-Chi Tsai ,  Chih-Ming Lee ,  Chi-Yen Lin ,  Kuo-Hung Lo

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/423 ,  H10B10/00 ,  G11C11/412 ,  H01L27/02

CPC classification number: H10B10/12 ,  H01L21/823475 ,  H01L29/0649 ,  H01L29/4238 ,  G11C11/412 ,  H01L27/0207

Abstract: An IC structure includes a first gate strip and a first active region under the first gate strip and forming a first transistor with the first gate strip. From a top view, the first active region has opposite short sides and opposite long sides connecting the short sides and longer than the short sides. First one of the long sides has a first stepped top-view profile. Second one of the long sides has a second stepped top-view profile. The first stepped top-view profile has more step rises than the second stepped top-view profile.

公开(公告)号：US11462550B2

公开(公告)日：2022-10-04

申请号：US16994900

申请日：2020-08-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Gulbagh Singh ,  Shun-Chi Tsai ,  Chih-Ming Lee ,  Chi-Yen Lin ,  Kuo-Hung Lo

IPC: H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8234 ,  G11C11/412 ,  H01L27/02

Abstract: An SRAM structure includes first and second gate strips extending along a first direction. A first active region extends across the first gate strip from a top view, and forms a first pull-up transistor with the first gate strip. A second active region extends across the second gate strip from the top view, and forms a second pull-up transistor with the second gate strip. From the top view the first active region has a first stepped sidewall facing away from the second active region. The first stepped sidewall has a first side surface farthest from the second active region, a second side surface set back from the first side surface along the first direction, and a third side surface set back from the second side surface along the first direction.

公开(公告)号：US10734489B2

公开(公告)日：2020-08-04

申请号：US16179165

申请日：2018-11-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gulbagh Singh ,  Cheng-Yeh Huang ,  Chin-Nan Chang ,  Chih-Ming Lee ,  Chi-Yen Lin

IPC: H01L29/40 ,  H01L21/762 ,  H01L21/768 ,  H01L21/324 ,  H01L29/45 ,  H01L21/265

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate. The method includes forming an isolation structure in the semiconductor substrate. The isolation structure surrounds a first active region and a second active region of the semiconductor substrate. The method includes forming a semiconductor strip structure over the semiconductor substrate. The semiconductor strip structure extends across the first active region, the second active region, and the isolation structure between the first active region and the second active region, the semiconductor strip structure has a P-type doped region, an N-type doped region, and a spacing region. The method includes performing an implantation process over the spacing region. The method includes forming a metal silicide layer over the semiconductor strip structure to cover the P-type doped region, the N-type doped region, and the spacing region.

公开(公告)号：US10158004B2

公开(公告)日：2018-12-18

申请号：US15651344

申请日：2017-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsuing Chen ,  Ling-Sung Wang ,  Chi-Yen Lin

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L29/04 ,  H01L29/08 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L29/16

Abstract: Some embodiments of the present disclosure relates to a method of forming a semiconductor device having a strained channel and an associated device. In some embodiments, the method includes performing a first etching process by selectively exposing a substrate to a first etchant to produce a recess defined by sidewalls and a bottom surface of the substrate. An implantation process is performed to form an etch stop layer along the bottom surface. A second etching process is performed by exposing the sidewalls and the bottom surface defining the recess to a second etchant to form a source/drain recess. The source/drain recess laterally extends past the etch stop layer in opposing directions. A semiconductor material is formed within the source/drain recess.

公开(公告)号：US20160254366A1

公开(公告)日：2016-09-01

申请号：US15151663

申请日：2016-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsuing Chen ,  Ling-Sung Wang ,  Chi-Yen Lin

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/16 ,  H01L21/265 ,  H01L21/02 ,  H01L29/165 ,  H01L21/306 ,  H01L29/08

CPC classification number: H01L29/66636 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/30604 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/7848

Abstract: Some embodiments of the present disclosure relates to a method of forming a transistor device having a strained channel and an associated device. In some embodiments, the method is performed by performing a first etch of a substrate to produce a recess having a largest width at an opening along a top surface of the substrate. An etch stop layer is formed by doping a bottom surface of the recess with a dopant. A second etch of the recess is then performed to form a source/drain recess, wherein the etch stop layer resists etching of the second etch. A stress inducing material is formed within the source/drain recess onto the etch stop layer.

Abstract translation: 本公开的一些实施例涉及形成具有应变通道和相关联的器件的晶体管器件的方法。 在一些实施例中，该方法是通过对衬底进行第一蚀刻来实现的，以在衬底的顶表面的开口处产生具有最大宽度的凹槽。 通过用掺杂剂掺杂凹陷的底表面形成蚀刻停止层。 然后执行凹陷的第二蚀刻以形成源极/漏极凹部，其中蚀刻停止层抵抗对第二蚀刻的蚀刻。 在源极/漏极凹槽内形成应力诱导材料到蚀刻停止层上。

公开(公告)号：US09385215B2

公开(公告)日：2016-07-05

申请号：US14182777

申请日：2014-02-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsuing Chen ,  Ling-Sung Wang ,  Chi-Yen Lin

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/04 ,  H01L29/08

CPC classification number: H01L29/66636 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/30604 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/7848

Abstract: Some embodiments of the present disclosure relates to a method and a device to achieve a strained channel. A volume of a source or drain recess is controlled by a performing an etch of a substrate to produce a recess. An anisotropic etch stop layer is then formed by doping a bottom surface of the recess with a boron-containing dopant, which distorts the crystalline structure of the bottom surface. An anisotropic etch of the recess is then performed. The anisotropic etch stop layer resists anisotropic etching such that the recess comprises a substantially flat bottom surface after the anisotropic etch. The source or drain recess is then filled with a stress-inducing material to produce a strained channel.

Abstract translation: 本公开的一些实施例涉及实现应变信道的方法和装置。 通过对衬底进行蚀刻来产生凹陷来控制源极或漏极凹槽的体积。 然后通过用含硼掺杂剂掺杂凹部的底表面来形成各向异性蚀刻停止层，其使得底表面的晶体结构发生变形。 然后进行凹陷的各向异性蚀刻。 各向异性蚀刻停止层抵抗各向异性蚀刻，使得凹陷在各向异性蚀刻之后包括基本平坦的底表面。 然后用引发应力的材料填充源极或漏极凹槽以产生应变通道。

公开(公告)号：US20140295630A1

公开(公告)日：2014-10-02

申请号：US14305427

申请日：2014-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsuing Chen ,  Ling-Sung Wang ,  Chi-Yen Lin

IPC: H01L21/8238 ,  H01L29/165

CPC classification number: H01L21/823814 ,  H01L21/76895 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/1104 ,  H01L29/0688 ,  H01L29/165 ,  H01L29/7848

Abstract: The present disclosure relates to a method for fabricating a butted a contact arrangement configured to couple two transistors, wherein an active region of a first transistor is coupled to a gate of a second transistor. The gate of the second transistor is formed from a gate material which comprises a dummy gate of the first transistor, and is configured to straddle a boundary between the active region of the first transistor and an isolation layer formed about the first transistor. The butted a contact arrangement results in a decreased contact resistance for the butted contact as compared to previous methods.

Abstract translation: 本公开涉及一种用于制造对接的配置成耦合两个晶体管的接触装置的方法，其中第一晶体管的有源区耦合到第二晶体管的栅极。 第二晶体管的栅极由包括第一晶体管的伪栅极的栅极材料形成，并且被配置为跨越第一晶体管的有源区域和围绕第一晶体管形成的隔离层之间的边界。 与之前的方法相比，对接的接触布置导致对接触点的接触电阻降低。