公开(公告)号：US20230068965A1

公开(公告)日：2023-03-02

申请号：US17459494

申请日：2021-08-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hung CHU ,  Shuen-Shin LIANG ,  Hsu-Kai CHANG ,  Tzu Pei CHEN ,  Kan-Ju LIN ,  Chien CHANG ,  Hung-Yi HUANG ,  Sung-Li WANG

IPC: H01L29/45 ,  H01L29/417 ,  H01L23/532 ,  H01L29/40 ,  H01L21/311 ,  H01L21/8234

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a layer of dielectric material over the gate structure, a source/drain (S/D) contact layer formed through and adjacent to the gate structure, and a trench conductor layer over and in contact with the S/D contact layer. The S/D contact layer can include a layer of platinum-group metallic material and a silicide layer formed between the substrate and the layer of platinum-group metallic material. A top width of a top portion of the layer of platinum-group metallic material can be greater than or substantially equal to a bottom width of a bottom portion of the layer of platinum-group metallic material.

公开(公告)号：US20230061022A1

公开(公告)日：2023-03-02

申请号：US17459799

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsu-Kai CHANG ,  Chia-Hung CHU ,  Shuen-Shin LIANG ,  Keng-Chu LIN ,  Pinyen LIN ,  Sung-Li WANG

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a source/drain (S/D) contact structure adjacent to the gate structure, a layer of dielectric material over the S/D contact structure and over the gate structure, a layer of organometallic material formed through the layer of dielectric material, and a trench conductor layer formed through the layer of dielectric material and in contact with the S/D contact structure and the gate structure. The layer of organometallic material can be between the layer of dielectric material and the trench conductor layer.

公开(公告)号：US20220293760A1

公开(公告)日：2022-09-15

申请号：US17472540

申请日：2021-09-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsungyu HUNG ,  Pang-Yen TSAI ,  Ding-Kang SHIH ,  Sung-Li WANG ,  Chia-Hung CHU

IPC: H01L29/423 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/786 ,  H01L29/66

Abstract: Low-resistance contacts improve performance of integrated circuit devices that feature epitaxial source/drain regions. The low resistance contacts can be used with transistors of various types, including planar field effect transistors (FETs), FinFETs, and gate-all-around (GAA) FETs. Low-resistance junctions are formed by removing an upper portion of the source/drain region and replacing it with an epitaxially-grown boron-doped silicon germanium (SiGe) material. Material resistivity can be tuned by varying the temperature during the epitaxy process. Electrical contact is then made at the low-resistance junctions.

公开(公告)号：US20210376103A1

公开(公告)日：2021-12-02

申请号：US16887577

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing, Co., Ltd.

Inventor： Shuen-Shin LIANG ,  Chun-I TSAI ,  Chih-Wei CHANG ,  Chun-Hsien HUANG ,  Hung-Yi HUANG ,  Keng-Chu LIN ,  Ken-Yu CHANG ,  Sung-Li WANG ,  Chia-Hung CHU ,  Hsu-Kai CHANG

IPC: H01L29/45 ,  H01L23/535 ,  H01L21/768

Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes forming a liner-free conductive structure on a cobalt conductive structure disposed on a substrate, depositing a cobalt layer on the liner-free conductive structure and exposing the liner-free conductive structure to a heat treatment. The method further includes removing the cobalt layer from the liner-free conductive structure.

公开(公告)号：US20210226057A1

公开(公告)日：2021-07-22

申请号：US16744480

申请日：2020-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hung CHU ,  Sung-Li WANG ,  Fang-Wei LEE ,  Jung-Hao CHANG ,  Mrunal Abhijith KHADERBAD ,  Keng-Chu LIN

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/45 ,  H01L21/311 ,  H01L29/417

Abstract: A method for forming a fin field effect transistor device structure includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes growing a source/drain epitaxial structure over the fin structure. The method also includes depositing a first dielectric layer surrounding the source/drain epitaxial structure. The method also includes forming a contact structure in the first dielectric layer over the source/drain epitaxial structure. The method also includes depositing a second dielectric layer over the first dielectric layer. The method also includes forming a hole in the second dielectric layer to expose the contact structure. The method also includes etching the contact structure to enlarge the hole in the contact structure. The method also includes filling the hole with a conductive material.

公开(公告)号：US20240096998A1

公开(公告)日：2024-03-21

申请号：US18516373

申请日：2023-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuen-Shin LIANG ,  Chij-chien CHI ,  Yi-Ying LIU ,  Chia-Hung CHU ,  Hsu-Kai CHANG ,  Cheng-Wei CHANG ,  Chein-Shun LIAO ,  Keng-chu LIN ,  KAi-Ting HUANG

IPC: H01L29/45 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H01L29/78

CPC classification number: H01L29/45 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76882 ,  H01L21/76895 ,  H01L23/53209 ,  H01L23/535 ,  H01L29/7851

Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.

公开(公告)号：US20230221645A1

公开(公告)日：2023-07-13

申请号：US18114690

申请日：2023-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hsuan CHUANG ,  Po-Sheng LU ,  Shou-Wen KUO ,  Cheng-Yi HUANG ,  Chia-Hung CHU

IPC: G03F7/16 ,  H01L21/027 ,  G03F7/004

CPC classification number: G03F7/162 ,  H01L21/0273 ,  G03F7/0048

Abstract: A multi-spray RRC process with dynamic control to improve final yield and further reduce resist cost is disclosed. In one embodiment, a method, includes: dispensing a first layer of solvent on a semiconductor substrate while spinning at a first speed for a first time period; dispensing the solvent on the semiconductor substrate while spinning at a second speed for a second time period so as to transform the first layer to a second layer of the solvent; dispensing the solvent on the semiconductor substrate While spinning at a third speed for a third time period so as to transform the second layer to a third layer of the solvent; dispensing the solvent on the semiconductor substrate while spinning at a fourth speed for a fourth time period so as to transform the third layer to a fourth layer of the solvent; and dispensing a first layer of photoresist on the fourth layer of the solvent while spinning at a fifth speed for a fifth period of time.

公开(公告)号：US20230012147A1

公开(公告)日：2023-01-12

申请号：US17371245

申请日：2021-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hung CHU ,  Ding-Kang SHIH ,  Keng-Chu LIN ,  Pang-Yen TSAI ,  Sung-Li WANG ,  Shuen-Shin LIANG ,  Tsungyu HUNG ,  Hsu-Kai CHANG

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/40 ,  H01L21/285

Abstract: The present disclosure describes a method to form a semiconductor device with backside contact structures. The method includes forming a semiconductor device on a first side of a substrate. The semiconductor device includes a source/drain (S/D) region. The method further includes etching a portion of the S/D region on a second side of the substrate to form an opening and forming an epitaxial contact structure on the S/D region in the opening. The second side is opposite to the first side. The epitaxial contact structure includes a first portion in contact with the S/D region in the opening and a second portion on the first portion. A width of the second portion is larger than the first portion.

公开(公告)号：US20220384601A1

公开(公告)日：2022-12-01

申请号：US17818918

申请日：2022-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Hsu-Kai CHANG ,  Jhih-Rong HUANG ,  Yen-Tien TUNG ,  Chia-Hung CHU ,  Shuen-Shin LIANG ,  Tzer-Min SHEN ,  Pinyen LIN ,  Sung-Li WANG

IPC: H01L29/45 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/78

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

公开(公告)号：US20210407925A1

公开(公告)日：2021-12-30

申请号：US16950537

申请日：2020-11-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei CHANG ,  Chien-Shun LIAO ,  Sung-Li WANG ,  Shuen-Shin LIANG ,  Shu-Lan CHANG ,  Yi-Ying LIU ,  Chia-Hung CHU ,  Hsu-Kai CHANG

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact.