公开(公告)号：US20240088261A1

公开(公告)日：2024-03-14

申请号：US18516410

申请日：2023-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Peng-Wei CHU ,  Yasutoshi OKUNO ,  Ding-Kang SHIH ,  Sung-Li WANG

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/165 ,  H01L29/45

CPC classification number: H01L29/665 ,  H01L21/0206 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/6656 ,  H01L21/02576 ,  H01L21/02579

Abstract: The structure of a semiconductor device with dual silicide contact structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming first and second fin structures on a substrate, forming first and second epitaxial regions on the first and second fin structures, respectively, forming first and second contact openings on the first and second epitaxial regions, respectively, selectively forming an oxide capping layer on exposed surfaces of the second epitaxial region, selectively forming a first metal silicide layer on exposed surfaces of the first epitaxial region, removing the oxide capping layer, and forming first and second conductive regions on the metal silicide layer and on the exposed surfaces of the second epitaxial region, respectively. The first metal silicide layer includes a first metal. The first and second conductive regions includes a second metal different from the first metal.

公开(公告)号：US20250113517A1

公开(公告)日：2025-04-03

申请号：US18477648

申请日：2023-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-An WANG ,  Ding-Kang SHIH ,  Chia-Ling PAI ,  Pinyen LIN

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A method of forming source/drain regions of semiconductor devices is disclosed. The method includes forming a fin structure on a substrate, forming a polysilicon structure on the fin structure, removing a portion of the fin structure adjacent to the polysilicon structure to form an opening, and forming a S/D region in the opening. The forming the S/D region includes exposing the fin structure in the opening to a first flow rate of a precursor gas during a first phase of a gas flow cycle, a second flow rate of the precursor gas during a second phase of the gas flow cycle. The exposing the fin structure in the opening to the precursor gas, the etching gas, and the plasma is performed in an in-situ process.

公开(公告)号：US20230061755A1

公开(公告)日：2023-03-02

申请号：US17463123

申请日：2021-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ding-Kang SHIH ,  Pang-Yen TSAI

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/06

Abstract: The present disclosure provides channel structures of a semiconductor device and fabricating methods thereof. The method can include forming a superlattice structure with first nanostructured layers and second nanostructured layers on a fin structure. The method can also include removing the second nanostructured layers to form multiple gate openings; forming a germanium epitaxial growth layer on the first nanostructured layers at a first temperature and a first pressure; and increasing the first temperature to a second temperature and increasing the first pressure to a second pressure over a first predetermined period of time. The method can further include annealing the germanium epitaxial growth layer at the second temperature and the second pressure in the chamber over a second predetermined period of time to form a cladding layer surrounding the first nanostructured layers.

公开(公告)号：US20230031490A1

公开(公告)日：2023-02-02

申请号：US17738759

申请日：2022-05-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ding-Kang SHIH ,  Chung-Liang Cheng ,  Pang-Yen Tsai

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66 ,  H01L21/84

Abstract: A strain-relaxed silicon/silicon germanium (Si/SiGe) bi-layer can be used as a foundation for constructing strained channel transistors in the form of nanosheet gate all-around field effect transistors (GAAFETs). The bi-layer can be formed using a modified silicon-on-insulator process. A superlattice can then be epitaxially grown on the bi-layer to provide either compressively strained SiGe channels for a p-type metal oxide semiconductor (PMOS) device, or tensile-strained silicon channels for an n-type metal oxide semiconductor (NMOS) device. Composition and strain of the bi-layer can influence performance of the strained channel devices.

公开(公告)号：US20220293760A1

公开(公告)日：2022-09-15

申请号：US17472540

申请日：2021-09-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsungyu HUNG ,  Pang-Yen TSAI ,  Ding-Kang SHIH ,  Sung-Li WANG ,  Chia-Hung CHU

IPC: H01L29/423 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/786 ,  H01L29/66

Abstract: Low-resistance contacts improve performance of integrated circuit devices that feature epitaxial source/drain regions. The low resistance contacts can be used with transistors of various types, including planar field effect transistors (FETs), FinFETs, and gate-all-around (GAA) FETs. Low-resistance junctions are formed by removing an upper portion of the source/drain region and replacing it with an epitaxially-grown boron-doped silicon germanium (SiGe) material. Material resistivity can be tuned by varying the temperature during the epitaxy process. Electrical contact is then made at the low-resistance junctions.

公开(公告)号：US20230387262A1

公开(公告)日：2023-11-30

申请号：US18232159

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ding-Kang SHIH ,  Pang-Yen TSAI

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/0665 ,  H01L21/823431 ,  H01L29/785

Abstract: The present disclosure provides channel structures of a semiconductor device and fabricating methods thereof. The method can include forming a superlattice structure with first nanostructured layers and second nanostructured layers on a fin structure. The method can also include removing the second nanostructured layers to form multiple gate openings; forming a germanium epitaxial growth layer on the first nanostructured layers at a first temperature and a first pressure; and increasing the first temperature to a second temperature and increasing the first pressure to a second pressure over a first predetermined period of time. The method can further include annealing the germanium epitaxial growth layer at the second temperature and the second pressure in the chamber over a second predetermined period of time to form a cladding layer surrounding the first nanostructured layers.

公开(公告)号：US20230012147A1

公开(公告)日：2023-01-12

申请号：US17371245

申请日：2021-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hung CHU ,  Ding-Kang SHIH ,  Keng-Chu LIN ,  Pang-Yen TSAI ,  Sung-Li WANG ,  Shuen-Shin LIANG ,  Tsungyu HUNG ,  Hsu-Kai CHANG

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/40 ,  H01L21/285

Abstract: The present disclosure describes a method to form a semiconductor device with backside contact structures. The method includes forming a semiconductor device on a first side of a substrate. The semiconductor device includes a source/drain (S/D) region. The method further includes etching a portion of the S/D region on a second side of the substrate to form an opening and forming an epitaxial contact structure on the S/D region in the opening. The second side is opposite to the first side. The epitaxial contact structure includes a first portion in contact with the S/D region in the opening and a second portion on the first portion. A width of the second portion is larger than the first portion.