公开(公告)号：US20240243009A1

公开(公告)日：2024-07-18

申请号：US18618815

申请日：2024-03-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sung-Li WANG ,  Shuen-Shin LIANG ,  Yu-Yun PENG ,  Fang-Wei LEE ,  Chia-Hung CHU ,  Mrunal Abhijith KHADERBAD ,  Keng-Chu LIN

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/285 ,  H01L21/306 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76816 ,  H01L21/02063 ,  H01L21/02068 ,  H01L21/28562 ,  H01L21/30604 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266

Abstract: A device includes source/drain regions, a gate structure, a source/drain contact, and a tungsten structure. The source/drain regions are over a substrate. The gate structure is between the source/drain regions. The source/drain contact is over one of the source/drain regions. The tungsten structure is over the source/drain contact. The tungsten structure includes a lower portion and an upper portion above the lower portion. The upper portion has opposite sidewalls respectively set back from opposite sidewalls of the lower portion of the tungsten structure.

公开(公告)号：US20230163169A1

公开(公告)日：2023-05-25

申请号：US18158148

申请日：2023-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei CHANG ,  Shuen-Shin LIANg ,  Sung-Li WANG ,  Hsu-Kai CHANG ,  Chia-Hung CHU ,  Chien-Shun LIAO ,  Yi-Ying LIU

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/0665 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/41733 ,  H01L29/1033

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and methods of fabricating the same are disclosed. The semiconductor device includes first and second S/D regions, a nanostructured channel region disposed between the first and second S/D regions, a gate structure surrounding the nanostructured channel region, first and second contact structures disposed on first surfaces of the first and second S/D regions, a third contact structure disposed on a second surface of the first S/D region, and an etch stop layer disposed on a second surface of the second S/D region. The third contact structure includes a metal silicide layer, a silicide nitride layer disposed on the metal silicide layer, and a conductive layer disposed on the silicide nitride layer.

公开(公告)号：US20230095976A1

公开(公告)日：2023-03-30

申请号：US18061676

申请日：2022-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuen-Shin LIANG ,  Chun-I TSAI ,  Chih-Wei CHANG ,  Chun-Hsien HUANG ,  Hung-Yi HUANG ,  Keng-Chu LIN ,  Ken-Yu CHANG ,  Sung-Li WANG ,  Chia-Hung CHU ,  Hsu-Kai CHANG

IPC: H01L23/532 ,  H01L21/768

Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.

公开(公告)号：US20210335720A1

公开(公告)日：2021-10-28

申请号：US17141445

申请日：2021-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuen-Shin LIANG ,  Chun-I TSAI ,  Chih-Wei CHANG ,  Chun-Hsien HUANG ,  Hung-Yi HUANG ,  Keng-Chu LIN ,  Ken-Yu CHANG ,  Sung-Li WANG ,  Chia-Hung CHU ,  Hsu-Kai CHANG

IPC: H01L23/532 ,  H01L21/768

Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.

公开(公告)号：US20210193511A1

公开(公告)日：2021-06-24

申请号：US16721762

申请日：2019-12-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sung-Li WANG ,  Shuen-Shin LIANG ,  Yu-Yun PENG ,  Fang-Wei LEE ,  Chia-Hung CHU ,  Mrunal Abhijith KHADERBAD ,  Keng-Chu LIN

IPC: H01L21/768 ,  H01L21/306

Abstract: A multi-layer interconnect structure with a self-aligning barrier structure and a method for fabricating the same is disclosed. For example, the method includes forming a via through an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and a contact structure, pre-cleaning the via with a metal halide, forming a barrier structure on the contact structure in-situ during the pre-cleaning of the via with the metal halide, and depositing a second metal in the via on top of the barrier structure.

公开(公告)号：US20240371952A1

公开(公告)日：2024-11-07

申请号：US18770393

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hung CHU ,  Tsungyu Hung ,  Hsu-Kai Chang ,  Ding-Kang Shih ,  Keng-Chu Lin ,  Pang-Yen Tsai ,  Sung-Li Wang ,  Shuen-Shin Liang

IPC: H01L29/417 ,  H01L21/285 ,  H01L29/40 ,  H01L29/423

Abstract: The present disclosure describes a method to form a semiconductor device with backside contact structures. The method includes forming a semiconductor device on a first side of a substrate. The semiconductor device includes a source/drain (S/D) region. The method further includes etching a portion of the S/D region on a second side of the substrate to form an opening and forming an epitaxial contact structure on the S/D region in the opening. The second side is opposite to the first side. The epitaxial contact structure includes a first portion in contact with the S/D region in the opening and a second portion on the first portion. A width of the second portion is larger than the first portion.

公开(公告)号：US20230016100A1

公开(公告)日：2023-01-19

申请号：US17815730

申请日：2022-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsu-Kai CHANG ,  Keng-Chu LIN ,  Sung-Li WANG ,  Shuen-Shin LIANG ,  Chia-Hung CHU

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening that exposes a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally under the etch stop layer. The method further includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.

公开(公告)号：US20220139773A1

公开(公告)日：2022-05-05

申请号：US17575444

申请日：2022-01-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sung-Li WANG ,  Shuen-Shin LIANG ,  Yu-Yun PENG ,  Fang-Wei LEE ,  Chia-Hung CHU ,  Mrunal Abhijith KHADERBAD ,  Keng-Chu LIN

IPC: H01L21/768 ,  H01L21/306 ,  H01L23/522 ,  H01L21/285 ,  H01L21/02 ,  H01L23/532

Abstract: An IC structure includes a transistor, a source/drain contact, a metal oxide layer, a non-metal oxide layer, a barrier structure, and a via. The transistor includes a gate structure and source/drain regions on opposite sides of the gate structure. The source/drain contact is over one of the source/drain regions. The metal oxide layer is over the source/drain contact. The non-metal oxide layer is over the metal oxide layer. The barrier structure is over the source/drain contact. The barrier structure forms a first interface with the metal oxide layer and a second interface with the non-metal oxide layer, and the second interface is laterally offset from the first interface. The via extends through the non-metal oxide layer to the barrier structure.

公开(公告)号：US20220037500A1

公开(公告)日：2022-02-03

申请号：US17197892

申请日：2021-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Li WANG ,  Hsu-Kai CHANG ,  Jhih-Rong HUANG ,  Yen-Tien TUNG ,  Chia-Hung CHU ,  Tzer-Min SHEN ,  Pinyen LIN

IPC: H01L29/45 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L21/285 ,  H01L29/66

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a gate structure disposed on the fin structure, a source/drain (S/D) region disposed adjacent to the gate structure, a contact structure disposed on the S/D region, and a dipole layer disposed at an interface between the ternary compound layer and the S/D region. The contact structure includes a ternary compound layer disposed on the S/D region, a work function metal (WFM) silicide layer disposed on the ternary compound layer, and a contact plug disposed on the WFM silicide layer.

公开(公告)号：US20230386912A1

公开(公告)日：2023-11-30

申请号：US18232718

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsu-Kai CHANG ,  Chia-Hung CHU ,  Shuen-Shin LIANG ,  Keng-Chu LIN ,  Pinyen LIN ,  Sung-Li WANG

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76844 ,  H01L23/5226 ,  H01L23/53266 ,  H01L21/76816 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/76876

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a source/drain (S/D) contact structure adjacent to the gate structure, a layer of dielectric material over the S/D contact structure and over the gate structure, a layer of organometallic material formed through the layer of dielectric material, and a trench conductor layer formed through the layer of dielectric material and in contact with the S/D contact structure and the gate structure. The layer of organometallic material can be between the layer of dielectric material and the trench conductor layer.