公开(公告)号：US20220367455A1

公开(公告)日：2022-11-17

申请号：US17815185

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting PAN ,  Yi-Ruei JHAN ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: According to one example, a method includes forming a first set of fin structures on a substrate, forming a sacrificial material between fin structures within the first set of fin structures, forming a dummy gate with a planar bottom surface over the fin structures and the sacrificial material, forming sidewall structures on the dummy gate, laterally etching the sacrificial material underneath the sidewall structures, depositing a lower sidewall structure where the sacrificial material was removed, removing the dummy gate, removing the sacrificial material, and forming a real gate over the fin structures.

公开(公告)号：US20220328478A1

公开(公告)日：2022-10-13

申请号：US17481668

申请日：2021-09-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Ruei JHAN ,  Kuan-Ting PAN ,  Kuo-Cheng CHIANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/66

Abstract: A device includes a substrate, a first semiconductor channel over the substrate, and a second semiconductor channel over the substrate laterally offset from the first semiconductor channel. A first gate structure and a second gate structure are over and laterally surround the first and second semiconductor channels, respectively. A first inactive fin is between the first gate structure and the second gate structure. A dielectric feature over the inactive fin includes multiple layers of dielectric material formed through alternating deposition and etching steps.

公开(公告)号：US20220068716A1

公开(公告)日：2022-03-03

申请号：US17005172

申请日：2020-08-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuan-Ting PAN ,  Kuo-Cheng CHIANG ,  Shi-Ning JU ,  Shang-Wen CHANG ,  Chih-Hao WANG

IPC: H01L21/8234 ,  H01L27/088

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first fin, a second fin adjacent the first fin, and a third fin adjacent the second fin. The structure further includes a first source/drain epitaxial feature merged with a second source/drain epitaxial feature. The structure further includes a third source/drain epitaxial feature, and a first liner positioned at a first distance away from a first plane defined by a first sidewall of the first fin and a second distance away from a second plane defined by a second sidewall of the second fin. The first distance is substantially the same as the second distance, and the merged first and second source/drain epitaxial features is disposed over the first liner. The structure further includes a dielectric feature disposed between the second source/drain epitaxial feature and the third source/drain epitaxial feature.

公开(公告)号：US20200328208A1

公开(公告)日：2020-10-15

申请号：US16910574

申请日：2020-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHIANG ,  Shi-Ning JU ,  Chih-Hao WANG ,  Kuan-Ting PAN ,  Zhi-Chang LIN

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation structure formed over a substrate, and a first stacked structure and a second stacked structure extending above the isolation structure. The first stacked structure includes a plurality of first nanostructures stacked in a vertical direction, and the second stacked structure includes a plurality of second nanostructures stacked in the vertical direction. The semiconductor device structure also includes a first dummy fin structure formed over the isolation structure, and the first dummy fin structure is between the first fin structure and the second fin structure. The semiconductor device structure includes a capping layer formed over the first dummy fin structure, and a top surface of the capping layer is higher than a top surface of the first stacked structure and a top surface of the second stacked structure.

公开(公告)号：US20200258999A1

公开(公告)日：2020-08-13

申请号：US16858891

申请日：2020-04-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Shi-Ning JU ,  Kuan-Ting PAN ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/308 ,  H01L29/78 ,  H01L29/161 ,  H01L29/16 ,  H01L29/08 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/311

Abstract: Structures and formation methods of a semiconductor device structure are provided. The formation method includes forming a fin structure over a semiconductor substrate and forming a first isolation feature in the fin structure. The formation method also includes forming a second isolation feature over the semiconductor substrate after the formation of the first isolation feature. The fin structure and the first isolation feature protrude from the second isolation feature. The formation method further includes forming gate stacks over the second isolation feature, wherein the gate stacks surround the fin structure and the first isolation feature.

公开(公告)号：US20200243665A1

公开(公告)日：2020-07-30

申请号：US16260483

申请日：2019-01-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Zhi-Chang LIN ,  Kuan-Ting PAN ,  Chih-Hao WANG ,  Shi-Ning JU

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/033 ,  H01L27/088

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure extending above an isolation structure. The semiconductor device structure includes a dummy fin structure formed over the isolation structure, and the dummy fin structure is between the first fin structure and the second fin structure. The semiconductor device structure includes a capping layer formed over the dummy fin structure, and the top surface of the capping layer is higher than the top surface of the first fin structure and the top surface of the second fin structure. The semiconductor device structure includes a first gate structure formed over first fin structure, and a second gate structure formed over the second fin structure. The first gate structure and the second gate structure are separated by the dummy fin structure and the capping layer.

公开(公告)号：US20200127124A1

公开(公告)日：2020-04-23

申请号：US16226827

申请日：2018-12-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Kuan-Ting PAN ,  Shi-Ning JU ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

Abstract: A method for forming a FinFET device structure includes forming a first fin structure in a core region of a substrate and a second fin structure in an input/output region of the substrate with a fin top layer and a hard mask layer over the fin structures. The method also includes forming a dummy oxide layer across the fin structures. The method also includes forming a dummy gate structure over the dummy oxide layer. The method also includes removing the dummy gate structure over fin structures. The method also includes removing the dummy oxide layer and trimming the fin structures. The method also includes forming first and second oxide layers across the first and second fin structures. The method also includes forming first and second gate structures over the first and second oxide layers across the first and second fin structures.

公开(公告)号：US20230282749A1

公开(公告)日：2023-09-07

申请号：US18316541

申请日：2023-05-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Kuan-Ting PAN ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/16 ,  H01L21/8234

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L27/0886 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/66545 ,  H01L21/823431

Abstract: A method includes forming a SiGe layer over a substrate. A silicon layer is formed over the SiGe layer. The silicon layer and the SiGe layer are patterned to form a fin structure over the substrate. The fin structure includes a remaining portion of the SiGe layer and a remaining portion of the silicon layer over the remaining portion of the SiGe layer. A semiconductive capping layer is formed to cover the fin structure. A top portion of the semiconductive capping layer and the remaining portion of the silicon layer are oxidized to form an oxide layer covering the fin structure.

公开(公告)号：US20230014998A1

公开(公告)日：2023-01-19

申请号：US17379936

申请日：2021-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shi-Ning JU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG ,  Kuan-Lun CHENG ,  Guan-Lin CHEN ,  Kuan-Ting PAN

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234

Abstract: A device includes a substrate, a first semiconductor channel over the substrate, a second semiconductor channel over the substrate and laterally offset from the first semiconductor channel, and a third semiconductor channel over the substrate and laterally offset from the second semiconductor channel. A first gate structure, a second gate structure, and a third gate structure are over and lateral surround the first, second, and third semiconductor channels, respectively. A first inactive fin is between the first gate structure and the second gate structure, and a second inactive fin is between the second gate structure and the third gate structure. A bridge conductor layer is over the first, second, and third gate structures, and the first and second inactive fins. A dielectric plug extends from an upper surface of the second inactive fin, through the bridge conductor layer, to at least an upper surface of the bridge conductor layer.

公开(公告)号：US20220093595A1

公开(公告)日：2022-03-24

申请号：US17027322

申请日：2020-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuan-Ting PAN ,  Kuo-Cheng CHIANG ,  Shi-Ning JU ,  Yi-Ruei JHAN ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L27/092 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a semiconductor fin including a first surface, a second surface opposite the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The semiconductor device structure further includes a gate electrode layer disposed adjacent the first, third, and fourth surfaces of the semiconductor fin, a first source/drain epitaxial feature in contact with the semiconductor fin, and a first inner spacer disposed between the first source/drain epitaxial feature and the gate electrode layer. The first inner spacer is in contact with the first source/drain epitaxial feature, and the first inner spacer comprises a first material. The semiconductor device structure further includes a first spacer in contact with the first inner spacer, and the first spacer comprises a second material different from the first material.