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公开(公告)号:US11043731B2
公开(公告)日:2021-06-22
申请号:US16671182
申请日:2019-11-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Nan-Chin Chuang , Chen-Hua Yu , Chung-Shi Liu , Chao-Wen Shih , Shou-Zen Chang
IPC: H01Q1/22 , H01Q21/00 , H01Q19/30 , H01L23/552 , H01L23/66 , H01L23/00 , H01Q21/24 , H01L23/31 , H01Q1/52 , H01Q15/14 , H01Q21/28
Abstract: A package structure including a first redistribution circuit structure, a semiconductor die, first antennas and second antennas is provided. The semiconductor die is located on and electrically connected to the first redistribution circuit structure. The first antennas and the second antennas are located over the first redistribution circuit structure and electrically connected to the semiconductor die through the first redistribution circuit structure. A first group of the first antennas are located at a first position, a first group of the second antennas are located at a second position, and the first position is different from the second position in a stacking direction of the first redistribution circuit structure and the semiconductor die.
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公开(公告)号:US20200067173A1
公开(公告)日:2020-02-27
申请号:US16671182
申请日:2019-11-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Nan-Chin Chuang , Chen-Hua Yu , Chung-Shi Liu , Chao-Wen Shih , Shou-Zen Chang
IPC: H01Q1/22 , H01L23/31 , H01Q21/24 , H01Q21/00 , H01L23/552 , H01L23/00 , H01L23/66 , H01Q1/52 , H01Q19/30
Abstract: A package structure including a first redistribution circuit structure, a semiconductor die, first antennas and second antennas is provided. The semiconductor die is located on and electrically connected to the first redistribution circuit structure. The first antennas and the second antennas are located over the first redistribution circuit structure and electrically connected to the semiconductor die through the first redistribution circuit structure. A first group of the first antennas are located at a first position, a first group of the second antennas are located at a second position, and the first position is different from the second position in a stacking direction of the first redistribution circuit structure and the semiconductor die.
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公开(公告)号:US10483617B2
公开(公告)日:2019-11-19
申请号:US15879456
申请日:2018-01-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Nan-Chin Chuang , Chen-Hua Yu , Chung-Shi Liu , Chao-Wen Shih , Shou-Zen Chang
IPC: H01Q1/22 , H01L23/66 , H01L23/31 , H01L23/00 , H01L23/552 , H01Q21/00 , H01Q21/24 , H01Q1/52 , H01Q19/30 , H01Q15/14 , H01Q21/28
Abstract: A package structure including an insulating encapsulation, at least one semiconductor die, at least one first antenna and at least one second antenna is provided. The insulating encapsulation includes a first portion, a second portion and a third portion, wherein the second portion is located between the first portion and the third portion. The at least one semiconductor die is encapsulated in the first portion of the insulating encapsulation, and the second portion and the third portion are stacked on the at least one semiconductor die. The at least one first antenna is electrically connected to the at least one semiconductor die and encapsulated in the third portion of the insulating encapsulation. The at least one second antenna is electrically connected to the at least one semiconductor die and encapsulated in the second portion of the insulating encapsulation.
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公开(公告)号:US11004810B2
公开(公告)日:2021-05-11
申请号:US16714768
申请日:2019-12-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Kai-Chiang Wu , Chun-Lin Lu , Chao-Wen Shih , Han-Ping Pu , Nan-Chin Chuang
IPC: H01L23/66 , H01L23/538 , H01L21/48 , H01L21/56 , H01Q21/06 , H01Q1/22 , H01L23/31 , H01L21/683 , H01Q21/28 , H01Q1/40
Abstract: A semiconductor package structure including an encapsulation body, an RFIC chip, a first antenna structure, and a second antenna structure is provided. The RFIC chip may be embedded in the encapsulation body. The first antenna structure may be disposed at a lateral side of the RFIC chip, electrically connected to the RFIC chip, and include a first conductor layer and a plurality of first patches opposite to the first conductor layer. The second antenna structure may be stacked on the RFIC chip, electrically connected to the RFIC chip, and include a second conductor layer and a plurality of second patches opposite to the second conductor layer. The first patches and the second patches are located at a surface of the encapsulation body. A first distance between the first conductor layer and the first patches is different from a second distance between the second conductor layer and the second patches.
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公开(公告)号:US20200058607A1
公开(公告)日:2020-02-20
申请号:US16661972
申请日:2019-10-23
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Albert Wan , Chao-Wen Shih , Shou-Zen Chang , Nan-Chin Chuang
IPC: H01L23/66 , H01L23/31 , H01Q9/30 , H01Q1/40 , H01Q1/22 , H01L21/683 , H01L21/56 , H01L23/00 , H01L23/60 , H01L23/48
Abstract: A package structure include a ground plate, a semiconductor die, a molding compound, and an antenna element. The semiconductor die is located over the ground plate. The molding compound is located over the semiconductor die. The antenna element is located in the molding compound and overlaps with the ground plate along a stacking direction of the ground plate, the semiconductor die and the molding compound. The antenna element has a first side levelled with a first surface of the molding compound, and the ground plate is located between the semiconductor die and the antenna element.
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公开(公告)号:US10510693B2
公开(公告)日:2019-12-17
申请号:US15717940
申请日:2017-09-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Kai-Chiang Wu , Chun-Lin Lu , Chao-Wen Shih , Han-Ping Pu , Nan-Chin Chuang
Abstract: A semiconductor package structure including an encapsulation body, an RFIC chip, a first antenna structure, and a second antenna structure is provided. The RFIC chip may be embedded in the encapsulation body. The first antenna structure may be disposed at a lateral side of the RFIC chip, electrically connected to the RFIC chip, and include a first conductor layer and a plurality of first patches opposite to the first conductor layer. The second antenna structure may be stacked on the RFIC chip, electrically connected to the RFIC chip, and include a second conductor layer and a plurality of second patches opposite to the second conductor layer. The first patches and the second patches are located at a surface of the encapsulation body. A first distance between the first conductor layer and the first patches is different from a second distance between the second conductor layer and the second patches.
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公开(公告)号:US10475757B2
公开(公告)日:2019-11-12
申请号:US16252728
申请日:2019-01-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Albert Wan , Chao-Wen Shih , Shou-Zen Chang , Nan-Chin Chuang
IPC: H01L23/66 , H01L23/00 , H01L23/48 , H01L23/31 , H01L23/60 , H01L21/56 , H01L21/683 , H01Q1/22 , H01Q1/40 , H01Q9/30 , H01L21/66
Abstract: A package structure includes at least one die, an antenna element, and at least one through interlayer via. The antenna element is located on the at least one die. The at least one through interlayer via is located between the antenna element and the at least one die, wherein the antenna element is electrically connected to the at least one die through the at least one through interlayer via.
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公开(公告)号:US20190027449A1
公开(公告)日:2019-01-24
申请号:US15652249
申请日:2017-07-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Albert Wan , Chao-Wen Shih , Shou-Zen Chang , Nan-Chin Chuang
Abstract: A package structure includes at least one die, an antenna element, and at least one through interlayer via. The antenna element is located on the at least one die. The at least one through interlayer via is located between the antenna element and the at least one die, wherein the antenna element is electrically connected to the at least one die through the at least one through interlayer via.
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公开(公告)号:US10186492B1
公开(公告)日:2019-01-22
申请号:US15652249
申请日:2017-07-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Albert Wan , Chao-Wen Shih , Shou-Zen Chang , Nan-Chin Chuang
IPC: H01L23/66 , H01L23/00 , H01L23/48 , H01L23/31 , H01L23/60 , H01L21/56 , H01L21/683 , H01Q1/22 , H01L21/66
Abstract: A package structure includes at least one die, an antenna element, and at least one through interlayer via. The antenna element is located on the at least one die. The at least one through interlayer via is located between the antenna element and the at least one die, wherein the antenna element is electrically connected to the at least one die through the at least one through interlayer via.
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