公开(公告)号：US20200058627A1

公开(公告)日：2020-02-20

申请号：US16103925

申请日：2018-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shing-Chao Chen ,  Ching-Hua Hsieh ,  Chih-Wei Lin ,  Sheng-Chieh Yang

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: A package includes a first redistribution structure, a bridge structure, an adhesive layer, a plurality of conductive pillars, an encapsulant, a first die, and a second die. The bridge structure is disposed on the first redistribution structure. The adhesive layer is disposed between the bridge structure and the first redistribution structure. The conductive pillars surround the bridge structure. A height of the conductive pillars is substantially equal to a sum of a height of the adhesive layer and a height of the bridge structure. The encapsulant encapsulates the bridge structure, the adhesive layer, and the conductive pillars. The first die and the second die are disposed over the bridge structure. The first die is electrically connected to the second die through the bridge structure. The first die and the second die are electrically connected to the first redistribution structure through the conductive pillars.

公开(公告)号：US10283470B2

公开(公告)日：2019-05-07

申请号：US15599480

申请日：2017-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Shing-Chao Chen ,  Ching-Hua Hsieh ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Meng-Tse Chen ,  Sheng-Hsiang Chiu ,  Sheng-Feng Weng

IPC: H01L23/28 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a chip, a molding compound, and a dielectric layer. The chip has a connector thereon. The molding compound encapsulates the chip, wherein a surface of the molding compound is substantially lower than an active surface of the chip. The dielectric layer is disposed over the chip and the molding compound, wherein the dielectric layer has a planar surface, and a material of the dielectric layer is different from a material of the molding compound.

公开(公告)号：US20190096840A1

公开(公告)日：2019-03-28

申请号：US15715132

申请日：2017-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ai-Tee Ang ,  Shing-Chao Chen ,  Ching-Hua Hsieh ,  Chih-Wei Lin ,  Ching-Yao Lin

IPC: H01L23/00 ,  H01L21/683 ,  H01L21/56

Abstract: An integrated fan-out package includes a first and second dies, an encapsulant, and a redistribution structure. The first and second dies respectively has an active surface, a rear surface opposite to the active surface, and conductive posts on the active surface. The first and second dies are different types of dies. The active and rear surfaces of the first die are respectively levelled with the active and rear surfaces of the second die. Top surfaces of the conductive posts of the first and second dies are levelled. The conductive posts of the first and second dies are wrapped by same material. The encapsulant encapsulates sidewalls of the first and second dies. A first surface of the encapsulant is levelled with the active surfaces. The second surface of the encapsulant is levelled with the rear surfaces. The redistribution structure is disposed over the first die, the second die, and the encapsulant.