公开(公告)号：US20210057259A1

公开(公告)日：2021-02-25

申请号：US16547605

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chieh Yang ,  Shing-Chao Chen ,  Ching-Hua Hsieh ,  Chih-Wei Lin

IPC: H01L21/683 ,  H01L21/82 ,  H01L21/56 ,  H01L23/00

Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor wafer having an active side and a back side opposite to the active side is provided. A plurality of conductive bumps are provided on the active side. A protection film is laminated on the active side, wherein the protection film includes a dielectric film covering the plurality of conductive bumps and a cover film covering the dielectric film. A thinning process is performed on the back side to form a thinned semiconductor wafer. The cover film is removed from the dielectric film. A singularization process is performed on the thinned semiconductor wafer with the dielectric film to form a plurality of semiconductor devices.

公开(公告)号：US09947552B2

公开(公告)日：2018-04-17

申请号：US15195321

申请日：2016-06-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shing-Chao Chen ,  Chih-Wei Lin ,  Meng-Tse Chen ,  Hui-Min Huang ,  Ming-Da Cheng ,  Kuo-Lung Pan ,  Wei-Sen Chang ,  Tin-Hao Kuo ,  Hao-Yi Tsai

IPC: H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/58

CPC classification number: H01L21/566 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/315 ,  H01L23/585 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/18162 ,  H01L2224/83 ,  H01L2224/81

Abstract: Structures and formation methods of a chip package are provided. The method includes forming multiple conductive structures over a carrier substrate and disposing a semiconductor die over the carrier substrate. The method also includes disposing a mold over the carrier substrate. The method further includes forming a protection layer between the mold and the carrier substrate to surround the semiconductor die and the conductive structures. In addition, the method includes removing the mold.

公开(公告)号：US10515900B2

公开(公告)日：2019-12-24

申请号：US16222047

申请日：2018-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shing-Chao Chen ,  Chih-Wei Lin ,  Tsung-Hsien Chiang ,  Ming-Da Cheng ,  Ching-Hua Hsieh

IPC: H01L23/495 ,  H01L23/538 ,  H01L21/48 ,  H01L21/683 ,  H01L21/56 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

Abstract: A chip package is provided. The chip package includes a semiconductor die and a protection layer surrounding the semiconductor die. The chip package also includes a dielectric layer over the semiconductor die and the protection layer. The dielectric layer has an upper surface with cutting scratches. The chip package further includes a conductive layer over the dielectric layer and filling some of the cutting scratches.

公开(公告)号：US20190252339A1

公开(公告)日：2019-08-15

申请号：US16396782

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ai-Tee Ang ,  Shing-Chao Chen ,  Ching-Hua Hsieh ,  Chih-Wei Lin ,  Ching-Yao Lin

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L24/19 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L24/11 ,  H01L24/24 ,  H01L24/25 ,  H01L24/96 ,  H01L2221/68331 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/1191 ,  H01L2224/18 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/25171 ,  H01L2224/73209 ,  H01L2224/95001

Abstract: A manufacturing method of integrated fan-out package includes following steps. First and second dies are provided on adhesive layer formed on carrier. Heights of first and second dies are different. First and second dies respectively has first and second conductive posts each having substantially a same height. The dies are pressed against adhesive layer to make active surfaces thereof be in direct contact with adhesive layer and conductive posts thereof be submerged into adhesive layer. Adhesive layer is cured. Encapsulant is formed to encapsulate the dies. Carrier is removed from adhesive layer. Heights of first and second conductive posts are reduced and portions of the adhesive layer is removed. First and second conductive posts are laterally wrapped by and exposed from adhesive layer. Top surfaces of first and second conductive posts are leveled. Redistribution structure is formed over adhesive layer and is electrically connected to first and second conductive posts.

公开(公告)号：US10276537B2

公开(公告)日：2019-04-30

申请号：US15715132

申请日：2017-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ai-Tee Ang ,  Shing-Chao Chen ,  Ching-Hua Hsieh ,  Chih-Wei Lin ,  Ching-Yao Lin

IPC: H01L27/00 ,  H01L23/00 ,  H01L21/683 ,  H01L21/56 ,  H01L21/00

Abstract: An integrated fan-out package includes a first and second dies, an encapsulant, and a redistribution structure. The first and second dies respectively has an active surface, a rear surface opposite to the active surface, and conductive posts on the active surface. The first and second dies are different types of dies. The active and rear surfaces of the first die are respectively leveled with the active and rear surfaces of the second die. Top surfaces of the conductive posts of the first and second dies are leveled. The conductive posts of the first and second dies are wrapped by same material. The encapsulant encapsulates sidewalls of the first and second dies. A first surface of the encapsulant is leveled with the active surfaces. The second surface of the encapsulant is leveled with the rear surfaces. The redistribution structure is disposed over the first die, the second die, and the encapsulant.

公开(公告)号：US10157846B2

公开(公告)日：2018-12-18

申请号：US15292762

申请日：2016-10-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shing-Chao Chen ,  Chih-Wei Lin ,  Tsung-Hsien Chiang ,  Ming-Da Cheng ,  Ching-Hua Hsieh

IPC: H01L21/44 ,  H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L21/683 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31

Abstract: Structures and formation methods of a chip package are provided. The method includes disposing a semiconductor die over a carrier substrate and forming a protection layer over the carrier substrate to surround the semiconductor die. The method also includes forming a dielectric layer over the protection layer and the semiconductor die. The method further includes cutting an upper portion of the dielectric layer to improve flatness of the dielectric layer. In addition, the method includes forming a conductive layer over the dielectric layer after cutting the upper portion of the dielectric layer.

公开(公告)号：US20180337149A1

公开(公告)日：2018-11-22

申请号：US15599480

申请日：2017-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Shing-Chao Chen ,  Ching-Hua Hsieh ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Meng-Tse Chen ,  Sheng-Hsiang Chiu ,  Sheng-Feng Weng

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768

CPC classification number: H01L24/05 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76885 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L2224/05008

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a chip, a molding compound, and a dielectric layer. The chip has a connector thereon. The molding compound encapsulates the chip, wherein a surface of the molding compound is substantially lower than an active surface of the chip. The dielectric layer is disposed over the chip and the molding compound, wherein the dielectric layer has a planar surface, and a material of the dielectric layer is different from a material of the molding compound.

公开(公告)号：US10128193B2

公开(公告)日：2018-11-13

申请号：US15413690

申请日：2017-01-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shing-Chao Chen ,  Chih-Wei Lin ,  Ching-Yao Lin ,  Ming-Da Cheng ,  Ching-Hua Hsieh

IPC: H01L21/4763 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/10

Abstract: A package structure and methods for forming the same are provided. The package structure includes an integrated circuit die in a package layer. The package structure also includes a first passivation layer covering the package layer and the integrated circuit die, and a second passivation layer over the first passivation layer. The package structure further includes a seed layer and a conductive layer in the second passivation layer. The seed layer covers the top surface of the first passivation layer and extends into the first passivation layer. The conductive layer covers the seed layer and extends into the first passivation layer. In addition, the package structure includes a third passivation layer covering the second passivation layer. The seed layer further extends from the top surface of the first passivation layer to the third passivation layer along a sidewall of the conductive layer.

公开(公告)号：US11177156B2

公开(公告)日：2021-11-16

申请号：US16547605

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chieh Yang ,  Shing-Chao Chen ,  Ching-Hua Hsieh ,  Chih-Wei Lin

IPC: H01L21/683 ,  H01L21/82 ,  H01L21/56 ,  H01L23/00

Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor wafer having an active side and a back side opposite to the active side is provided. A plurality of conductive bumps are provided on the active side. A protection film is laminated on the active side, wherein the protection film includes a dielectric film covering the plurality of conductive bumps and a cover film covering the dielectric film. A thinning process is performed on the back side to form a thinned semiconductor wafer. The cover film is removed from the dielectric film. A singularization process is performed on the thinned semiconductor wafer with the dielectric film to form a plurality of semiconductor devices.

公开(公告)号：US11088124B2

公开(公告)日：2021-08-10

申请号：US16103925

申请日：2018-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shing-Chao Chen ,  Ching-Hua Hsieh ,  Chih-Wei Lin ,  Sheng-Chieh Yang

IPC: H01L23/31 ,  H01L25/16 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: A package includes a first redistribution structure, a bridge structure, an adhesive layer, a plurality of conductive pillars, an encapsulant, a first die, and a second die. The bridge structure is disposed on the first redistribution structure. The adhesive layer is disposed between the bridge structure and the first redistribution structure. The conductive pillars surround the bridge structure. A height of the conductive pillars is substantially equal to a sum of a height of the adhesive layer and a height of the bridge structure. The encapsulant encapsulates the bridge structure, the adhesive layer, and the conductive pillars. The first die and the second die are disposed over the bridge structure. The first die is electrically connected to the second die through the bridge structure. The first die and the second die are electrically connected to the first redistribution structure through the conductive pillars.