-
公开(公告)号：US11446851B2
公开(公告)日：2022-09-20
申请号：US16398164
申请日：2019-04-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Sheng-Feng Weng , Ching-Hua Hsieh , Chung-Shi Liu , Chih-Wei Lin , Sheng-Hsiang Chiu , Yao-Tong Lai , Chia-Min Lin
Abstract: A molding apparatus is configured for molding a semiconductor device and includes a lower mold and an upper mold. The lower mold is configured to carry the semiconductor device. The upper mold is disposed above the lower mold for receiving the semiconductor device and includes a mold part and a dynamic part. The mold part is configured to cover the upper surface of the semiconductor device. The dynamic part is disposed around a device receiving region of the upper mold and configured to move relatively to the mold part. A molding method and a molded semiconductor device are also provided.
-
公开(公告)号：US20210193544A1
公开(公告)日：2021-06-24
申请号：US16719955
申请日：2019-12-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chia-Min Lin , Ching-Hua Hsieh , Chih-Wei Lin , Sheng-Hsiang Chiu , Sheng-Feng Weng , Yao-Tong Lai
IPC: H01L23/31 , H01L21/56 , H01L25/16 , H01L23/498 , H01L23/00
Abstract: Three-dimensional integrated circuit (3DIC) structures and methods of forming the same are provided. A 3DIC structure includes a semiconductor package, a first package substrate, a molded underfill layer and a thermal interface material. The semiconductor package is disposed over and electrically connected to the first package substrate through a plurality of first bumps. The semiconductor package includes at least one semiconductor die and an encapsulation layer aside the semiconductor die. The molded underfill layer surrounds the plurality of first bumps and a sidewall of the semiconductor package, and has a substantially planar top surface. The CTE of the molded underfill layer is different from the CTE of the encapsulation layer of the semiconductor package. The thermal interface material is disposed over the semiconductor package.
-
公开(公告)号：US20210020611A1
公开(公告)日：2021-01-21
申请号：US17063251
申请日：2020-10-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Da Tsai , Meng-Tse Chen , Sheng-Feng Weng , Sheng-Hsiang Chiu , Wei-Hung Lin , Ming-Da Cheng , Ching-Hua Hsieh , Chung-Shi Liu
IPC: H01L25/065 , H01L23/00 , H01L25/10 , H01L21/683 , H01L21/56 , H01L21/78 , H01L23/31 , H01L23/48 , H01L25/00
Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.
-
公开(公告)号：US10283377B1
公开(公告)日：2019-05-07
申请号：US15832742
申请日：2017-12-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Meng-Tse Chen , Ching-Hua Hsieh , Chung-Shi Liu , Chih-Wei Lin , Sheng-Hsiang Chiu , Yao-Tong Lai
Abstract: An integrated fan-out (InFO) package includes at least one die, a plurality of conductive structures, an encapsulant, an enhancement layer, and a redistribution structure. The die has an active surface and includes a plurality of conductive posts on the active surface. The conductive structures surround the die. The encapsulant partially encapsulates the die. The enhancement layer is over the encapsulant. A top surface of the enhancement layer is substantially coplanar with top surfaces of the conductive posts and the conductive structures. A material of the enhancement layer is different from a material of the encapsulant. A roughness of an interface between the encapsulant and the enhancement layer is larger than a roughness of the top surface of the enhancement layer. The redistribution structure is over the enhancement layer and is electrically connected to the conductive structures and the die.
-
公开(公告)号：US11309226B2
公开(公告)日：2022-04-19
申请号：US16719955
申请日：2019-12-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chia-Min Lin , Ching-Hua Hsieh , Chih-Wei Lin , Sheng-Hsiang Chiu , Sheng-Feng Weng , Yao-Tong Lai
IPC: H01L23/31 , H01L25/16 , H01L23/498 , H01L23/00 , H01L21/56
Abstract: Three-dimensional integrated circuit (3DIC) structures and methods of forming the same are provided. A 3DIC structure includes a semiconductor package, a first package substrate, a molded underfill layer and a thermal interface material. The semiconductor package is disposed over and electrically connected to the first package substrate through a plurality of first bumps. The semiconductor package includes at least one semiconductor die and an encapsulation layer aside the semiconductor die. The molded underfill layer surrounds the plurality of first bumps and a sidewall of the semiconductor package, and has a substantially planar top surface. The CTE of the molded underfill layer is different from the CTE of the encapsulation layer of the semiconductor package. The thermal interface material is disposed over the semiconductor package.
-
Patent Agency Ranking
公开(公告)号：US20180337149A1
公开(公告)日：2018-11-22
申请号：US15599480
申请日：2017-05-19
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Wei Lin , Shing-Chao Chen , Ching-Hua Hsieh , Chen-Hua Yu , Chung-Shi Liu , Meng-Tse Chen , Sheng-Hsiang Chiu , Sheng-Feng Weng
IPC: H01L23/00 , H01L23/522 , H01L23/31 , H01L21/56 , H01L21/768
CPC classification number: H01L24/05 , H01L21/486 , H01L21/56 , H01L21/76885 , H01L23/3107 , H01L23/49816 , H01L23/5389 , H01L24/03 , H01L2224/05008
Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a chip, a molding compound, and a dielectric layer. The chip has a connector thereon. The molding compound encapsulates the chip, wherein a surface of the molding compound is substantially lower than an active surface of the chip. The dielectric layer is disposed over the chip and the molding compound, wherein the dielectric layer has a planar surface, and a material of the dielectric layer is different from a material of the molding compound.
-
公开(公告)号：US11705409B2
公开(公告)日：2023-07-18
申请号：US16916066
申请日：2020-06-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Albert Wan , Ching-Hua Hsieh , Chao-Wen Shih , Han-Ping Pu , Meng-Tse Chen , Sheng-Hsiang Chiu
IPC: H01L23/66 , H01L23/522 , H01L23/31 , H01L21/56
CPC classification number: H01L23/66 , H01L21/565 , H01L23/3114 , H01L23/5226 , H01L2223/6677
Abstract: A semiconductor device including a chip package, a dielectric structure, and a first antenna pattern is provided. The dielectric structure is disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern is disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern.
-
8.发明申请公开(公告)号：US20200338796A1
公开(公告)日：2020-10-29
申请号：US16398164
申请日：2019-04-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Sheng-Feng Weng , Ching-Hua Hsieh , Chung-Shi Liu , Chih-Wei Lin , Sheng-Hsiang Chiu , Yao-Tong Lai , Chia-Min Lin
Abstract: A molding apparatus is configured for molding a semiconductor device and includes a lower mold and an upper mold. The lower mold is configured to carry the semiconductor device. The upper mold is disposed above the lower mold for receiving the semiconductor device and includes a mold part and a dynamic part. The mold part is configured to cover the upper surface of the semiconductor device. The dynamic part is disposed around a device receiving region of the upper mold and configured to move relatively to the mold part. A molding method and a molded semiconductor device are also provided.
-
公开(公告)号：US20190333877A1
公开(公告)日：2019-10-31
申请号：US15965995
申请日：2018-04-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Albert Wan , Ching-Hua Hsieh , Chao-Wen Shih , Han-Ping Pu , Meng-Tse Chen , Sheng-Hsiang Chiu
IPC: H01L23/66 , H01L23/522 , H01L21/56 , H01L23/31
Abstract: A semiconductor device including a chip package, a dielectric structure and a first antenna pattern is provided. The dielectric structure disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern. A manufacturing method of a semiconductor device is also provided.
-
公开(公告)号：US11955460B2
公开(公告)日：2024-04-09
申请号：US17063251
申请日：2020-10-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Da Tsai , Meng-Tse Chen , Sheng-Feng Weng , Sheng-Hsiang Chiu , Wei-Hung Lin , Ming-Da Cheng , Ching-Hua Hsieh , Chung-Shi Liu
IPC: H01L23/00 , H01L21/56 , H01L21/683 , H01L21/78 , H01L23/31 , H01L23/48 , H01L25/00 , H01L25/065 , H01L25/10
CPC classification number: H01L25/0657 , H01L21/563 , H01L21/565 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L23/3107 , H01L23/481 , H01L24/17 , H01L24/19 , H01L24/20 , H01L24/97 , H01L25/105 , H01L25/50 , H01L21/568 , H01L23/3128 , H01L2221/68327 , H01L2221/68354 , H01L2221/68368 , H01L2224/0237 , H01L2224/024 , H01L2224/04105 , H01L2224/12105 , H01L2224/13022 , H01L2224/13024 , H01L2224/16145 , H01L2224/81815 , H01L2225/06513 , H01L2225/06548 , H01L2225/1035 , H01L2225/1058 , H01L2924/06 , H01L2924/0635 , H01L2924/0665 , H01L2924/07025 , H01L2924/0715 , H01L2924/14 , H01L2924/18162 , H01L2924/19011 , H01L2924/19102 , H01L2924/3511
Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.
-
-
-
-
-
-
-
-
-
Search Results
16
records
(took 0.016 seconds)
