Patent search ap:("Taiwan Semiconductor Manufacturing Co. Page Ltd.") AND inv:"Meng-Tse Chen"

1.

发明授权
Package on package structure and method for forming the same 有权

公开(公告)号：US11264342B2

公开(公告)日：2022-03-01

申请号：US16733609

申请日：2020-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu , Chung-Shi Liu , Ming-Da Cheng , Mirng-Ji Lii , Meng-Tse Chen , Wei-Hung Lin

IPC: H01L23/00 , H01L21/56 , H01L25/10 , H01L23/31 , H01L25/03 , H01L25/00 , H01L23/498 , B23K35/00 , B23K35/02 , B23K35/22 , B23K35/26 , B23K35/36 , H01L25/065

Abstract: Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface.

2.

发明申请
PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME 审中-公开

公开(公告)号：US20190333870A1

公开(公告)日：2019-10-31

申请号：US15964091

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen , Ching-Hua Hsieh , Chung-Shi Liu , Chih-Wei Lin , Hao-Cheng Hou , Jung-Wei Cheng

IPC: H01L23/00 , H01L23/31 , H01L23/498 , H01L21/56 , H01L21/02 , H01L21/48

Abstract: A package structure including a semiconductor die, a warpage control layer, an insulating encapsulant and a redistribution layer is provided. The semiconductor die has an active surface and a backside surface opposite to the active surface. The warpage control layer is disposed on the backside surface of the semiconductor die, wherein the warpage control layer comprises a material having a Young's Modulus of 100 GPa or more. The insulating encapsulant is encapsulating the semiconductor die and the warpage control layer. The redistribution layer is located on the insulating encapsulant and over the active surface of the semiconductor die.

3.

发明授权
Package-on-package structure having polymer-based material for warpage control 有权

公开(公告)号：US10269763B2

公开(公告)日：2019-04-23

申请号：US15461796

申请日：2017-03-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen , Yu-Chih Liu , Hui-Min Huang , Wei-Hung Lin , Jing Ruei Lu , Ming-Da Cheng , Chung-Shi Liu

IPC: H01L25/065 , H01L23/29 , H01L23/00 , H01L25/00 , H01L23/31 , H01L21/56

Abstract: The present disclosure relates to a package-on-package structure providing mechanical strength and warpage control. In some embodiments, the package-on-package structure includes a first set of conductive elements coupling a first package component to a second package component. A first molding material is arranged on the first package component. The first molding material surrounds the first set of conductive elements and outer sidewalls of the second package component and has a top surface below a top surface of the second package component. The stacked integrated chip structure further includes a second set of conductive elements that couples the second package component to a third package component.

4.

发明申请
SEMICONDCUTOR PACKAGE AND MANUFACTURING METHOD THEREOF 审中-公开

公开(公告)号：US20180337149A1

公开(公告)日：2018-11-22

申请号：US15599480

申请日：2017-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin , Shing-Chao Chen , Ching-Hua Hsieh , Chen-Hua Yu , Chung-Shi Liu , Meng-Tse Chen , Sheng-Hsiang Chiu , Sheng-Feng Weng

IPC: H01L23/00 , H01L23/522 , H01L23/31 , H01L21/56 , H01L21/768

CPC classification number: H01L24/05 , H01L21/486 , H01L21/56 , H01L21/76885 , H01L23/3107 , H01L23/49816 , H01L23/5389 , H01L24/03 , H01L2224/05008

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a chip, a molding compound, and a dielectric layer. The chip has a connector thereon. The molding compound encapsulates the chip, wherein a surface of the molding compound is substantially lower than an active surface of the chip. The dielectric layer is disposed over the chip and the molding compound, wherein the dielectric layer has a planar surface, and a material of the dielectric layer is different from a material of the molding compound.

5.

发明申请
PACKAGE-ON-PACKAGE STRUCTURE HAVING POLYMER-BASED MATERIAL FOR WARPAGE CONTROL 审中-公开

公开(公告)号：US20170194289A1

公开(公告)日：2017-07-06

申请号：US15461796

申请日：2017-03-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen , Yu-Chih Liu , Hui-Min Huang , Wei-Hung Lin , Jing Ruei Lu , Ming-Da Cheng , Chung-Shi Liu

IPC: H01L25/065 , H01L23/29 , H01L23/00 , H01L25/00 , H01L21/56 , H01L23/31

CPC classification number: H01L25/0652 , H01L21/561 , H01L21/563 , H01L23/00 , H01L23/293 , H01L23/3121 , H01L23/562 , H01L24/17 , H01L25/0655 , H01L25/50 , H01L2224/16 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L2225/06513 , H01L2225/06517 , H01L2225/06555 , H01L2225/06582 , H01L2924/15311

Abstract: The present disclosure relates to a package-on-package structure providing mechanical strength and warpage control. In some embodiments, the package-on-package structure includes a first set of conductive elements coupling a first package component to a second package component. A first molding material is arranged on the first package component. The first molding material surrounds the first set of conductive elements and outer sidewalls of the second package component and has a top surface below a top surface of the second package component. The stacked integrated chip structure further includes a second set of conductive elements that couples the second package component to a third package component.

6.

发明申请
PACKAGE-ON-PACKAGE STRUCTURE HAVING POLYMER-BASED MATERIAL FOR WARPAGE CONTROL 有权
Title translation: 具有聚合物材料的包装封装结构进行温度控制

公开(公告)号：US20160247782A1

公开(公告)日：2016-08-25

申请号：US15143892

申请日：2016-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen , Yu-Chih Liu , Hui-Min Huang , Wei-Hung Lin , Jing Ruei Lu , Ming-Da Cheng , Chung-Shi Liu

IPC: H01L25/065 , H01L23/00 , H01L25/00

CPC classification number: H01L25/0652 , H01L21/561 , H01L21/563 , H01L23/00 , H01L23/293 , H01L23/3121 , H01L23/562 , H01L24/17 , H01L25/0655 , H01L25/50 , H01L2224/16 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L2225/06513 , H01L2225/06517 , H01L2225/06555 , H01L2225/06582 , H01L2924/15311

Abstract: A package on package structure providing mechanical strength and warpage control includes a first package component coupled to a second package component by a first set of conductive elements. A first polymer-comprising material is arranged between the first package component and the second package component. The first polymer-comprising material surrounds the first set of conductive elements and the second package component. A third package component is coupled to the second package component by a second set of conductive elements. An underfill is arranged on the second package component and surrounds the second set of conductive elements. The first polymer-comprising material extends past sidewalls of the underfill.

Abstract translation: 提供机械强度和翘曲控制的封装结构的封装结构包括通过第一组导电元件耦合到第二封装元件的第一封装元件。第一聚合物包含材料布置在第一包装部件和第二包装部件之间。第一含聚合物的材料包围第一组导电元件和第二封装元件。第三封装部件通过第二组导电元件耦合到第二封装部件。底部填充物布置在第二包装部件上并且包围第二组导电元件。第一含聚合物的材料延伸穿过底部填充物的侧壁。

7.

发明申请
PACKAGE STRUCTURE 审中-公开

公开(公告)号：US20200091090A1

公开(公告)日：2020-03-19

申请号：US16691512

申请日：2019-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen , Ching-Hua Hsieh , Chung-Shi Liu , Chih-Wei Lin , Hao-Cheng Hou , Jung-Wei Cheng

IPC: H01L23/00 , H01L23/31 , H01L23/498 , H01L21/48 , H01L21/56 , H01L21/02

Abstract: A package structure including a semiconductor die, a warpage control layer, an insulating encapsulant and a redistribution layer is provided. The semiconductor die has an active surface and a backside surface opposite to the active surface. The warpage control layer is disposed on the backside surface of the semiconductor die, wherein the warpage control layer comprises a material having a Young's Modulus of 100 GPa or more. The insulating encapsulant is encapsulating the semiconductor die and the warpage control layer. The redistribution layer is located on the insulating encapsulant and over the active surface of the semiconductor die.

8.

发明授权
Package on package structure and method for forming the same 有权

公开(公告)号：US10177104B2

公开(公告)日：2019-01-08

申请号：US15631436

申请日：2017-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu , Chung-Shi Liu , Ming-Da Cheng , Mirng-Ji Lii , Meng-Tse Chen , Wei-Hung Lin

IPC: H01L23/00 , H01L23/31 , H01L25/065 , H01L23/498 , H01L21/56 , H01L25/10 , H01L25/03 , H01L25/00 , B23K35/00 , B23K35/02 , B23K35/22 , B23K35/26 , B23K35/36

Abstract: Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface.