公开(公告)号：US20220376045A1

公开(公告)日：2022-11-24

申请号：US17882817

申请日：2022-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Hsin Yang ,  Jung-Chi Jeng ,  Ru-Shang Hsiao

IPC: H01L29/06 ,  H01L29/66 ,  H03M1/06 ,  H01L21/027 ,  H01L21/311

Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a substrate having a first area and a second area, a plurality of fin structures extending along a direction over the first area and the second area of the substrate, a first transistor and a second transistor in the first area, a first isolation structure disposed between the first transistor and the second transistor, a first isolation structure disposed between the first transistor and the second transistor, a third transistor and a fourth transistor in the second area, and a second isolation structure disposed between the third transistor and the fourth transistor. The first isolation structure includes a first width along the direction and the second isolation structure includes a second width along the direction. The second width is greater than the first width.

公开(公告)号：US20220238521A1

公开(公告)日：2022-07-28

申请号：US17230117

申请日：2021-04-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Hsin Yang ,  Jung-Chi Jeng ,  Ru-Shang Hsiao

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8234

Abstract: In an embodiment, a device includes: an isolation region on a substrate; a fin structure protruding from between adjacent portions of the isolation region, the fin structure including a plurality of fins and a mesa, a channel region of the fin structure having a first portion in the fins and having a second portion in the mesa, the fins and the mesa being a continuous semiconductor material, the mesa having a greater width than the fins; and a first gate structure on the fin structure, the first gate structure extending along the first portion of the channel region in the fins and extending along the second portion of the channel region in the mesa.

公开(公告)号：US20240387531A1

公开(公告)日：2024-11-21

申请号：US18786970

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Hsin Yang ,  Jung-Chi Jeng ,  Ru-Shang Hsiao

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first transistor in a first area and a second transistor in a second area. The first transistor includes a first gate structure extending lengthwise along a first direction, and a first gate spacer, a second gate spacer, and a third gate spacer over sidewalls of the first gate structure. The second transistor includes a second gate structure extending lengthwise along the first direction, and the first gate spacer and the third gate spacer over sidewalls of the second gate structure. The first gate spacer, the second gate spacer and the third gate spacer are of different compositions and the third gate spacer is directly on the first gate spacer in the second area.

公开(公告)号：US11699702B2

公开(公告)日：2023-07-11

申请号：US17025802

申请日：2020-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Hsin Yang ,  Jung-Chi Jeng ,  Ru-Shang Hsiao

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/41791 ,  H01L29/6681 ,  H01L29/785

Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first transistor in a first area and a second transistor in a second area. The first transistor includes a first gate structure extending lengthwise along a first direction, and a first gate spacer, a second gate spacer, and a third gate spacer over sidewalls of the first gate structure. The second transistor includes a second gate structure extending lengthwise along the first direction, and the first gate spacer and the third gate spacer over sidewalls of the second gate structure. The first gate spacer, the second gate spacer and the third gate spacer are of different compositions and the third gate spacer is directly on the first gate spacer in the second area.

公开(公告)号：US20220359719A1

公开(公告)日：2022-11-10

申请号：US17813652

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Hsin Yang ,  Jung-Chi Jeng ,  Ru-Shang Hsiao

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/3213

Abstract: Semiconductor devices and methods of forming the same are provided. An example method includes providing a workpiece including a first dummy gate stack and a second dummy gate stack in a first area of the workpiece, a third dummy gate stack and a fourth dummy gate stack in a second area of the workpiece, a hard mask layer over each of the first dummy gate stack, the second dummy gate stack, the third dummy gate stack, and the fourth dummy gate stack. The method further includes depositing a photoresist (PR) layer over the workpiece to form a first PR layer portion over the first area and a second PR layer portion over the second area; and selectively forming a first opening through the second PR layer portion over the third dummy gate stack and a second opening through the second PR layer portion over the fourth dummy gate stack.

公开(公告)号：US11469335B2

公开(公告)日：2022-10-11

申请号：US17159289

申请日：2021-01-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Hsin Yang ,  Jung-Chi Jeng ,  Ru-Shang Hsiao

IPC: H01L29/94 ,  H01L27/06 ,  H01L29/66 ,  H01L29/78

Abstract: Various embodiments of the present disclosure are directed towards a FinFET MOS capacitor. In some embodiments, the FinFET MOS capacitor comprises a substrate and a capacitor fin structure extending upwardly from an upper surface of the substrate. The capacitor fin structure comprises a pair of dummy source/drain regions separated by a dummy channel region and a capacitor gate structure straddling on the capacitor fin structure. The capacitor gate structure is separated from the capacitor fin structure by a capacitor gate dielectric.

公开(公告)号：US12283595B2

公开(公告)日：2025-04-22

申请号：US17655321

申请日：2022-03-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Hsin Yang ,  Ru-Shang Hsiao ,  Ching-Hwanq Su ,  Chen-Bin Lin ,  Wen-Hsin Chan

IPC: H01L27/092 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8238

Abstract: A structure includes a bulk semiconductor substrate, a first plurality of dielectric isolation regions over the bulk semiconductor substrate, a plurality of semiconductor fins protruding higher than the first plurality of dielectric isolation regions, a first gate stack on top surfaces and sidewalls of the plurality of semiconductor fins, a second plurality of dielectric isolation regions over the bulk semiconductor substrate, a mesa structure in the second plurality of dielectric isolation regions, and a second gate stack over the mesa structure. Top surfaces of the first gate stack and the second gate stack are coplanar with each other.

公开(公告)号：US12218134B2

公开(公告)日：2025-02-04

申请号：US17230117

申请日：2021-04-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Hsin Yang ,  Jung-Chi Jeng ,  Ru-Shang Hsiao

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/78

Abstract: In an embodiment, a device includes: an isolation region on a substrate; a fin structure protruding from between adjacent portions of the isolation region, the fin structure including a plurality of fins and a mesa, a channel region of the fin structure having a first portion in the fins and having a second portion in the mesa, the fins and the mesa being a continuous semiconductor material, the mesa having a greater width than the fins; and a first gate structure on the fin structure, the first gate structure extending along the first portion of the channel region in the fins and extending along the second portion of the channel region in the mesa.

公开(公告)号：US12119265B2

公开(公告)日：2024-10-15

申请号：US16942514

申请日：2020-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Hsin Yang ,  Jung-Chi Jeng ,  Ru-Shang Hsiao

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/308

CPC classification number: H01L21/823431 ,  H01L27/0886 ,  H01L21/3086

Abstract: Semiconductor devices and methods of forming the same are provided. In an embodiment, a semiconductor device includes a substrate including a core device region and an input/output (I/O) device region, a plurality of core devices in the core device region, each of the plurality of core devices including a first active region extending along a first direction, and a first plurality of input/output (I/O) transistors in the I/O device region, each of the first plurality of I/O transistors including a second active region extending along the first direction. The first active region includes a first width along a second direction perpendicular to the first direction and the second active region includes a second width along the second direction. The second width is greater than the first width.

公开(公告)号：US20230154922A1

公开(公告)日：2023-05-18

申请号：US17655321

申请日：2022-03-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Hsin Yang ,  Ru-Shang Hsiao ,  Ching-Hwanq Su ,  Chen-Bin Lin ,  Wen-Hsin Chan

IPC: H01L27/092 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L27/0924 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878

Abstract: A structure includes a bulk semiconductor substrate, a first plurality of dielectric isolation regions over the bulk semiconductor substrate, a plurality of semiconductor fins protruding higher than the first plurality of dielectric isolation regions, a first gate stack on top surfaces and sidewalls of the plurality of semiconductor fins, a second plurality of dielectric isolation regions over the bulk semiconductor substrate, a mesa structure in the second plurality of dielectric isolation regions, and a second gate stack over the mesa structure. Top surfaces of the first gate stack and the second gate stack are coplanar with each other.