公开(公告)号：US11652157B2

公开(公告)日：2023-05-16

申请号：US17706339

申请日：2022-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen Lo

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7851 ,  H01L2029/7858

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over the fin structure, a first inner spacer layer formed in the fin structure and adjacent to the gate structure, and a second inner spacer layer extending through the first inner spacer layer.

公开(公告)号：US11289586B2

公开(公告)日：2022-03-29

申请号：US16990865

申请日：2020-08-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen Lo

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over the fin structure, a first inner spacer layer formed in the fin structure and adjacent to the gate structure, and a second inner spacer layer extending through the first inner spacer layer.

公开(公告)号：US20250040238A1

公开(公告)日：2025-01-30

申请号：US18361152

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wei Lu ,  Kenichi Sano ,  Tze-Chung Lin ,  Fang-Wei Lee ,  Chia-Chien Kuang ,  Yi-Chen Lo ,  Fo-Ju Lin ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: In an embodiment, a device includes: lower semiconductor nanostructures including a first semiconductor material; a lower epitaxial source/drain region adjacent the lower semiconductor nanostructures, the lower epitaxial source/drain region having a first conductivity type; upper semiconductor nanostructures including a second semiconductor material, the second semiconductor material different from the first semiconductor material; and an upper epitaxial source/drain region adjacent the upper semiconductor nanostructures, the upper epitaxial source/drain region having a second conductivity type, the second conductivity type being opposite the first conductivity type.

公开(公告)号：US10164067B2

公开(公告)日：2018-12-25

申请号：US15644600

申请日：2017-07-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen Lo ,  Li-Te Lin ,  Yu-Lien Huang

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/768 ,  H01L29/423 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/04 ,  H01L21/8234 ,  H01L29/45

Abstract: A method for fabricating a semiconductor device includes forming a gate electrode structure over a first region of a semiconductor substrate, and selectively forming an oxide layer overlying the gate electrode structure by reacting a halide compound with oxygen to increase a height of the gate electrode structure. The halide compound may be silicon tetrachloride, and the oxide layer may be silicon dioxide. The gate electrode structure may be a dummy gate electrode, which is subsequently removed, and replaced with another gate electrode structure.

公开(公告)号：US10050149B1

公开(公告)日：2018-08-14

申请号：US15598717

申请日：2017-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Tsai-Chun Li ,  Ching-Feng Fu ,  Ming-Huan Tsai ,  D. T. Lee ,  Cheng-Hua Yang ,  Yi-Chen Lo

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L29/423

Abstract: A method of forming a semiconductor device includes forming a source/drain region and spacers on a substrate. The method further includes forming an etch stop layer on the spacers and the source/drain region and forming a gate structure between the spacers. The method further includes etching back the gate structure, etching back the spacers and the etch back layer, and forming a gate capping structure on the etched back gate structure, spacers, and etch stop layer.