公开(公告)号：US12272731B2

公开(公告)日：2025-04-08

申请号：US17134830

申请日：2020-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Ching-Feng Fu ,  Huan-Just Lin

IPC: H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423

Abstract: In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure is disposed over a substrate and includes a pair of source/drain regions and a gate electrode between the pair of source/drain regions. A lower inter-layer dielectric (ILD) layer is disposed over the pair of source/drain regions and surrounds the gate electrode. The gate electrode is recessed from top of the lower ILD layer. A gate capping layer is disposed on the gate electrode. The gate capping layer has a top surface aligned or coplanar with that of the lower ILD layer.

公开(公告)号：US12211937B2

公开(公告)日：2025-01-28

申请号：US18344176

申请日：2023-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Feng Fu ,  Guan-Ren Wang ,  Yun-Min Chang ,  Yu-Lien Huang

IPC: H01L29/78 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device and method of manufacture are provided which help to support contacts while material is removed to form air gaps. In embodiments a contact is formed with an enlarged base to help support overlying portions of the contact. In other embodiments a scaffold material may also be placed prior to the formation of the air gaps in order to provide additional support.

公开(公告)号：US20240222427A1

公开(公告)日：2024-07-04

申请号：US18442794

申请日：2024-02-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Guan-Ren Wang ,  Ching-Feng Fu

IPC: H01L29/06 ,  H01L21/764 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H10B10/00

CPC classification number: H01L29/0649 ,  H01L21/764 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/41791 ,  H10B10/12

Abstract: In an embodiment, a device includes: a first source/drain region; a second source/drain region; an inter-layer dielectric (ILD) layer over the first source/drain region and the second source/drain region; a first source/drain contact extending through the ILD layer, the first source/drain contact connected to the first source/drain region; a second source/drain contact extending through the ILD layer, the second source/drain contact connected to the second source/drain region; and an isolation feature between the first source/drain contact and the second source/drain contact, the isolation feature including a dielectric liner and a void, the dielectric liner surrounding the void.

公开(公告)号：US12009429B2

公开(公告)日：2024-06-11

申请号：US17872825

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Guan-Ren Wang ,  Ching-Feng Fu

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823443 ,  H01L21/823821 ,  H01L29/41791 ,  H01L29/4975 ,  H01L29/66795

Abstract: In an embodiment, a structure includes: a gate stack over a channel region of a substrate; a source/drain region adjacent the channel region; a first inter-layer dielectric (ILD) layer over the source/drain region; a silicide between the first ILD layer and the source/drain region, the silicide contacting a top surface of the source/drain region and a bottom surface of the source/drain region; and a first source/drain contact having a first portion and a second portion, the first portion of the first source/drain contact disposed between the silicide and the first ILD layer, the second portion of the first source/drain contact extending through the first ILD layer and contacting the silicide.

公开(公告)号：US11515165B2

公开(公告)日：2022-11-29

申请号：US16898655

申请日：2020-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Guan-Ren Wang ,  Ching-Feng Fu

IPC: H01L21/306 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

Abstract: In an embodiment, a structure includes: a contact etch stop layer (CESL) over a substrate; a fin extending through the CESL; an epitaxial source/drain region in the fin, the epitaxial source/drain region extending through the CESL; a silicide contacting upper facets of the epitaxial source/drain region; a source/drain contact contacting the silicide, lower facets of the epitaxial source/drain region, and a first surface of the CESL; and an inter-layer dielectric (ILD) layer surrounding the source/drain contact, the ILD layer contacting the first surface of the CESL.

公开(公告)号：US20220359650A1

公开(公告)日：2022-11-10

申请号：US17874732

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Guan-Ren Wang ,  Ching-Feng Fu

IPC: H01L29/06 ,  H01L27/11 ,  H01L27/092 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/764 ,  H01L29/417

Abstract: In an embodiment, a device includes: a first source/drain region; a second source/drain region; an inter-layer dielectric (ILD) layer over the first source/drain region and the second source/drain region; a first source/drain contact extending through the ILD layer, the first source/drain contact connected to the first source/drain region; a second source/drain contact extending through the ILD layer, the second source/drain contact connected to the second source/drain region; and an isolation feature between the first source/drain contact and the second source/drain contact, the isolation feature including a dielectric liner and a void, the dielectric liner surrounding the void.

公开(公告)号：US11355637B2

公开(公告)日：2022-06-07

申请号：US16917306

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Feng Fu ,  Guan-Ren Wang ,  Yun-Min Chang ,  Yu-Lien Huang

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/66

Abstract: A semiconductor device and method of manufacture are provided which help to support contacts while material is removed to form air gaps. In embodiments a contact is formed with an enlarged base to help support overlying portions of the contact. In other embodiments a scaffold material may also be placed prior to the formation of the air gaps in order to provide additional support.

公开(公告)号：US10050149B1

公开(公告)日：2018-08-14

申请号：US15598717

申请日：2017-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Tsai-Chun Li ,  Ching-Feng Fu ,  Ming-Huan Tsai ,  D. T. Lee ,  Cheng-Hua Yang ,  Yi-Chen Lo

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L29/423

Abstract: A method of forming a semiconductor device includes forming a source/drain region and spacers on a substrate. The method further includes forming an etch stop layer on the spacers and the source/drain region and forming a gate structure between the spacers. The method further includes etching back the gate structure, etching back the spacers and the etch back layer, and forming a gate capping structure on the etched back gate structure, spacers, and etch stop layer.

公开(公告)号：US09911805B2

公开(公告)日：2018-03-06

申请号：US15349100

申请日：2016-11-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei Cheng Wu ,  Kong-Pin Chang ,  Chia Ming Liang ,  Meng-Fang Hsu ,  Ching-Feng Fu ,  Shih-Ting Hung

IPC: H01L21/76 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7851

Abstract: Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.

公开(公告)号：US09812536B2

公开(公告)日：2017-11-07

申请号：US15215845

申请日：2016-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Feng Fu ,  Yu-Chan Yen ,  Chia-Ying Lee

IPC: H01L29/45 ,  H01L29/417 ,  H01L21/768 ,  H01L29/423 ,  H01L29/66 ,  H01L21/3105 ,  H01L29/78 ,  H01L29/165 ,  H01L21/02 ,  H01L21/311 ,  H01L21/321 ,  H01L29/08 ,  H01L29/267

CPC classification number: H01L29/41783 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/76879 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/4175 ,  H01L29/42364 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/7851

Abstract: The present disclosure relate to a method to an integrated chip having a source/drain self-aligned contact to a transistor or other semiconductor device. In some embodiments, the integrated chip has a pair of gate structures including a gate electrode arranged over a substrate and an insulating material arranged over the gate electrode. A source/drain region is arranged within the substrate between the pair of gate structures. An etch stop layer is arranged along sidewalls of the pair of gate structures and over the source/drain region, and a dielectric layer is over the insulating material. A source/drain contact is arranged over the insulating material and the etch stop layer and is separated from the sidewalls of the pair of gate structures by the etch stop layer. The source/drain contact is electrically coupled to the source/drain region.